Separate Ferroelectric Capacitor Memory Cells for Gate Stack Reliability
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Solution Overview
Problem
State-of-the-art ferroelectric (FE) memory cells face endurance issues due to integration of FE materials in gate stacks, which degrades dielectric buffer materials and causes charging at the FE-semiconductor interface, and require complex fabrication processes, increasing costs and hindering large-scale adoption.
Innovation Solution
FE memory cells with transistors and FE capacitors are designed such that the FE capacitors are separate from the gate stacks, allowing independent control of dielectric and ferroelectric areas, reducing polarization and depolarization fields, and simplifying fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FE materials are integrated in gate stacks, then memory cell functionality is achieved, but transistor reliability deteriorates due to dielectric buffer degradation and charging at FE-semiconductor interface
Solution Approach 1:
The memory cell is divided into two independent components: a transistor with its gate stack and a separate FE capacitor. The FE material is placed only in the capacitor, not in the transistor gate stack. This segmentation isolates the harmful effects to the capacitor region while preserving transistor reliability, as the transistor operates without direct exposure to FE material degradation effects.
Solution Approach 2:
The FE material is extracted from the transistor gate stack and placed exclusively in the capacitor. This removes the source of harmful interactions between FE material and the transistor's dielectric buffer, eliminating charging effects at the FE-semiconductor interface while maintaining the memory functionality through the capacitor's polarization state.
2Device complexity
If FE capacitors are separate from gate stacks, then fabrication process complexity is reduced, but device area increases
Solution Approach 1:
The separate FE capacitor and transistor are merged into a single memory cell structure through shared regions. The capacitor can share the bit line connection and substrate region with the transistor, reducing the overall area overhead despite the physical separation of FE material from the gate stack.
3Adaptability or versatility
If FE capacitors are separate from gate stacks, then independent control of dielectric and ferroelectric areas is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The shared bit line structure serves multiple functions: it connects to the transistor for read/write operations and also connects to the capacitor for storing the memory state. This multi-functionality reduces the need for additional dedicated connections, simplifying the overall layout and reducing alignment precision requirements despite the separate FE capacitor structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves transistor reliability, reduces fabrication costs, and enables the use of simple, low-cost processes, enhancing the performance and scalability of FE memory technology.
Implementation Method 1
a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode
Data Source
AI summary
Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.