Separate-Gate CFET Nanosheet Structure for Electrical Isolation

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Solution Overview

Problem

As semiconductor devices scale to smaller dimensions, particularly at the 5 nanometer production node and beyond, there is a need for increased effective channel width per footprint area in FinFET devices, which nanosheet technologies aim to address, but challenges arise in isolating and integrating complementary FET (CFET) devices effectively.

Innovation Solution

A semiconductor structure is designed with a first nanosheet device and a second nanosheet device separated by an isolation layer, along with distinct gate contacts for each, allowing for electrically isolated nFET and pFET structures within a CFET device, utilizing deposition, etching, and lithography processes to form separate gate-all-around configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If nanosheet devices are scaled to smaller dimensions to increase effective channel width per footprint area, then device integration density is improved, but electrical isolation between complementary FET structures becomes more difficult to achieve

Engineering Contradiction:

Improvedevice integration densityVSAvoidelectrical isolation

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent divides the CFET structure into separate nFET and pFET regions with distinct gate contacts, allowing independent control and isolation of each transistor type while maintaining high integration density through vertical stacking

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An isolation layer is introduced between the nFET and pFET structures to provide electrical isolation, preventing unwanted interaction between the complementary transistors while allowing both to occupy the same footprint area

Inventive Principle:

Principle #24Intermediary (Mediator)

2Power

If a common gate structure is formed wrapping around nanosheet layers to increase effective channel width, then drive current is improved, but electrical isolation between nFET and pFET channels deteriorates

Engineering Contradiction:

Improvedrive currentVSAvoidelectrical isolation

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The gate structure is segmented into separate gate contacts for nFET and pFET, with the nFET gate contact isolated from the pFET gate contact by an isolation layer, allowing each transistor to have its own controlled gate while maintaining high drive current through vertical stacking

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An isolation layer is positioned between the gate contacts of nFET and pFET to prevent electrical interaction, ensuring that the high drive current capability of the stacked structure does not compromise the electrical isolation between complementary channels

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12550371B2Separate gate complementary field-effect transistor

Publication Date: 2026.02.10 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor structure comprises a first nanosheet device having at least one first channel layer and a first gate, a second nanosheet device disposed above the first nanosheet device and having at least one second channel layer and a second gate, and an isolation layer disposed between the first nanosheet device and the second nanosheet device to electrically isolate the first nanosheet device and the second nanosheet device.