Separate Signal and PDN Interconnects for Shorter 3D IC Power Paths
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Solution Overview
Problem
Existing integrated circuits (ICs) face challenges with power signal routing congestion and increased path lengths, leading to loop inductance and direct current (DC) losses, particularly in three-dimensional ICs (3DICs), due to power signals being routed in shared interconnect structures with input/output (I/O) signals.
Innovation Solution
The implementation of separate signal and power distribution network (PDN) interconnect structures within ICs, where the PDN interconnect structure is disposed on the opposite side of the semiconductor layer from the signal interconnect structure, utilizing through-silicon vias to transfer power and I/O signals, allowing for reduced power distribution signal routing path lengths and facilitating integration of decoupling capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power signals are routed through shared interconnect structures with I/O signals in 3DICs, then signal routing is simplified, but power signal routing congestion and path lengths increase
Solution Approach 1:
The interconnect structure is segmented into separate signal interconnect structures and power distribution network (PDN) interconnect structures. The signal interconnect structure includes first metallization layers with first metal interconnects for I/O signal routing, while the PDN interconnect structure includes second metallization layers with second metal interconnects dedicated to power and ground routing. This segmentation eliminates routing congestion and reduces power signal path lengths by providing dedicated routing paths.
Solution Approach 2:
The patent utilizes vertical stacking of metallization layers to separate signal and power routing in the vertical dimension. The first metallization layers for signals and second metallization layers for power are disposed at different vertical levels, allowing both signal and power to be routed simultaneously without interference, effectively using the third dimension to resolve routing conflicts.
2Ease of manufacture
If power signals are routed through shared interconnect structures, then fabrication process is simplified, but loop inductance and DC power losses increase
Solution Approach 1:
The fabrication process is segmented into separate sequences for forming signal interconnects and PDN interconnects. The first metallization layers are formed with first metal interconnects using a first fabrication sequence, while the second metallization layers are formed with second metal interconnects using a second fabrication sequence. This allows optimization of each fabrication sequence independently, maintaining ease of manufacture while achieving reduced power losses through shorter, dedicated power routing paths.
3Loss of energy
If separate signal and PDN interconnect structures are implemented, then power distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The through-silicon vias (TSVs) serve multiple functions: they provide mechanical support for stacking the first and second semiconductor dies, enable electrical connection between the signal interconnect structure of the first die and the PDN interconnect structure of the second die, and facilitate both signal and power routing across die interfaces. This multi-functionality reduces the need for additional specialized structures, offsetting the complexity of having separate interconnect structures.
4Reliability
If TSVs are used to transfer power signals between separate PDN interconnect structures, then power distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The TSVs are formed and prepared in advance during the fabrication of the first semiconductor die, before the second semiconductor die is stacked onto it. The first metallization layers and first metal interconnects are formed with TSVs integrated into the structure, so that when the second die is stacked, the TSVs are already positioned and prepared to receive connections from the second die's PDN interconnect structure, simplifying the overall manufacturing process.
Data Source
AI summary
Integrated circuits (ICs) having a separate signal and power distribution network (PDN) interconnect structures for reduced power signal routing congestion and path lengths, and related three-dimensional (3D) ICs (3DICs) and fabrication methods. The IC includes a separate signal interconnect structure providing input/output (I/O) signal routing, and a PDN interconnect structure for providing power distribution signal routing. The signal interconnect structure is disposed on a first side of a semiconductor layer in the IC, and the PDN interconnect structure is disposed on a second side of the semiconductor layer opposite of the first side. In this manner, performance of semiconductor devices in the semiconductor layer can be improved, because power distribution signals do not have to be routed in a shared interconnect structure that is also used for routing I/O signals, which could otherwise congest and increase power distribution signal routing path lengths in the IC.