Separate Read and Program Registers for Parallel Memory Access
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Solution Overview
Problem
Current data storage systems face inefficiencies when performing mixed read and program operations sequentially, as they cannot occur in parallel, leading to increased time requirements for command completion.
Innovation Solution
The implementation of separate read data and program data registers, along with their respective cache registers, allows for parallel execution of read and program operations, enabling overlapping memory access and data transfer even with non-consecutive commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If read and program operations are performed sequentially using shared registers, then device complexity is reduced, but command completion time increases
Solution Approach 1:
The patent divides the register system into separate read registers (read data register, read cache register) and program registers (program data register, program cache register). This segmentation allows read and program operations to execute in parallel without interfering with each other, reducing command completion time while maintaining manageable device complexity through structured organization.
Solution Approach 2:
The patent introduces a temporal dimension to register usage by maintaining separate register sets for read and program operations. This allows operations to proceed simultaneously in different temporal streams, transforming a sequential execution model into a parallel execution model that reduces overall command completion time.
2Loss of time
If read and program operations execute in parallel with separate registers, then command completion time is reduced, but device complexity increases
Solution Approach 1:
The patent segments the register functionality into distinct read and program register sets, each with dedicated cache registers. This segmentation enables parallel execution of read and program operations, reducing command completion time. The segmentation is implemented in a way that maintains clear functional boundaries while allowing efficient parallel operation.
Solution Approach 2:
The patent designs the register system so that each register type (read data register, read cache register, program data register, program cache register) serves its specific function exclusively, creating a universal pattern where similar operations follow consistent addressing and control sequences. This multi-functional design at the architectural level simplifies control logic despite the increased number of registers.
3Device complexity
If mixed read-program commands are processed sequentially, then register management is simplified, but productivity decreases
Solution Approach 1:
The patent segments command processing into separate read command paths and program command paths, each managed by dedicated registers. This segmentation allows mixed read-program command sequences to be processed in parallel, significantly improving productivity and command processing throughput while maintaining simplified register management through clear functional separation.
Solution Approach 2:
The patent enables continuous useful action by allowing read operations and program operations to execute simultaneously without waiting for each other to complete. The separate register sets ensure that read commands and program commands can proceed in parallel, maintaining continuous productive operation and eliminating idle waiting time in mixed command sequences.
Data Source
AI summary
Implementations disclosed herein include a system and method of storing one or more data and program data in a memory, temporarily storing the one or more data and the program data in a cache, managing the one or more data from the memory and the cache in a read data register and a read cache register, and managing the program data from the memory and the cache in a program data register and a program cache register, wherein each of the read data register and the read cache register are separate from the program data register and the program cache register. Read operations are performed only with the read data register and the read cache register. Program operations are performed only with the program data register and the program cache register.