Separate Read-Only and Write-Read Caches for Memory Subsystems

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Solution Overview

Problem

Conventional memory sub-systems face performance issues due to the use of a single cache for both read and write operations, leading to increased latency and reduced endurance of memory components, especially when handling sequential and random memory access workloads, and data hazards occur when requests are not properly synchronized.

Innovation Solution

Implementing separate read-only and write-read caches with outstanding command queues and a priority scheduler to manage requests, allowing for in-order and out-of-order access based on workload type, reducing the number of requests to the backing store, and improving data throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single cache is used for both read and write operations, then device complexity is reduced, but performance and latency are worsened

Engineering Contradiction:
Improvecache structureVSAvoidmemory access latency
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent divides the single cache into separate read-only cache and write-read cache structures. This segmentation allows independent optimization of read and write operations, reducing contention and improving access latency for both operation types simultaneously.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a single cache is used for both read and write operations, then device complexity is reduced, but endurance of memory components is worsened

Engineering Contradiction:
Improvecache structureVSAvoidendurance of memory components
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

By segmenting the cache into read-only and write-read portions, the patent reduces the number of write operations to the backing store through write-back caching. This decreases wear on memory components and improves their endurance.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If requests are not properly synchronized, then device complexity is reduced, but data hazards occur

Engineering Contradiction:
Improverequest managementVSAvoiddata hazard prevention
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary structure (the separate cache hierarchies with priority schedulers) that mediates between read and write requests. This intermediary ensures proper synchronization and ordering of operations, preventing data hazards while maintaining manageable complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Speed

If separate read-only and write-read caches are implemented, then performance and endurance are improved, but device complexity increases

Engineering Contradiction:
Improvememory access performanceVSAvoidcache structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The write-read cache is designed to handle both read and write operations, providing multi-functionality that reduces the need for completely separate cache structures. This universal approach improves performance while limiting the increase in complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

5Reliability

If separate read-only and write-read caches are implemented, then endurance of memory components is improved, but device complexity increases

Engineering Contradiction:
Improveendurance of memory componentsVSAvoidcache structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the write-intensive operations into a separate write-read cache hierarchy, isolating them from the read-only cache. This extraction improves endurance by reducing backing store access while organizing complexity into manageable, functional segments.

Inventive Principle:
Principle #2Taking out (Extraction)

6Productivity

If in-order and out-of-order access is allowed based on workload type, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improvedata throughputVSAvoidrequest scheduling
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic scheduling that adapts to workload characteristics, allowing in-order or out-of-order processing based on conditions. This dynamic approach maximizes throughput while managing complexity through adaptive rather than static control logic.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10908821B2Use of outstanding command queues for separate read-only cache and write-read cache in a memory sub-system
Publication Date: 2021.02.02 MICRON TECHNOLOGY INC
  • US10908821B2 patent drawing
  • US10908821B2 patent drawing
  • US10908821B2 patent drawing

AI summary

A request to read data stored at a memory sub-system can be received. A determination can be made whether the data is stored at a cache of the memory sub-system. responsive to determining that the data is not stored at the cache of the memory sub-system, a determination can be made, by a processing device, of a queue of a set of queues to store the request with other read requests for the data stored at the memory sub-system. Each queue of the et of queues corresponds to a respective cache line of the cache. The request can be stored at the determined queue with the other read requests for the data stored at the memory sub-system.