Separate Source Line Structure for Resistive Memory
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Solution Overview
Problem
Semiconductor memory devices with a separate source line structure face challenges in reducing chip size while maintaining high operating speed and nonvolatile characteristics, as they require a high write voltage and have significant chip-size overhead due to separate source lines for each bit line.
Innovation Solution
The semiconductor device incorporates a resistive memory cell connected between a bit line and a source line, with a source-line voltage supply circuit, a reference current generation circuit, and a bit-line sense amplifier circuit that operates using separate source lines to read and write data efficiently, allowing for reduced chip size and lower write voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a separate source line structure is used for each bit line, then high operating speed and nonvolatile characteristics are maintained, but chip-size overhead increases significantly
Solution Approach 1:
The source lines are segmented into separate individual source lines for each bit line, allowing independent control and optimization of each source line's voltage and current characteristics, which enables high-speed operation while managing chip area through precise local control
Solution Approach 2:
The source line structure is made dynamic by enabling independent voltage control of each source line through separate voltage supply circuits, allowing the system to adapt source line voltages based on operational requirements to maintain high speed while reducing overall chip area
2Speed
If a separate source line structure is used for each bit line, then high operating speed is achieved, but write voltage becomes high
Solution Approach 1:
Each source line is provided with its own voltage supply circuit that can independently control the voltage level, allowing local optimization of write voltage for each bit line to achieve high-speed operation without requiring uniformly high write voltage across the entire memory array
Solution Approach 2:
The voltage parameter of each source line can be independently changed through separate voltage supply circuits, enabling the system to adjust write voltages dynamically based on specific operational needs to maintain high speed while reducing write voltage requirements
3Speed
If source lines are respectively provided for all bit lines, then high operating speed is maintained, but device complexity increases
Solution Approach 1:
Each source line is designed with multi-functionality by integrating both read and write operations through a single source line structure, reducing the need for separate dedicated read and write source lines, thereby maintaining high operating speed while reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient data read and write operations with reduced chip size and power consumption, maintaining high operating speed and nonvolatile characteristics, while allowing for easier voltage control of source lines.
Implementation Method 1
A magnetic random access memory (MRAM) is a resistive memory, which is a type of nonvolatile semiconductor memory device, in which stored data is retained even if supply of power to the MRAM is stopped. In a MRAM, a data value stored in a cell thereof is determined according to whether a resistance value is high or low.
Implementation Method 2
a bit-line sense amplifier (S/A) circuit configured to sense and amplify the data stored in the resistive memory cell based on a comparison between cell current and the reference current, the cell current based on the data stored in the resistive memory cell
Data Source
AI summary
A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.