Separate-Well Voltage Tracking Circuit for Compact ESD Immunity
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Solution Overview
Problem
The miniaturization of integrated circuits has increased their susceptibility to electrostatic discharge (ESD) due to thinner dielectric thicknesses and lower dielectric breakdown voltages, leading to potential electronic circuit damage.
Innovation Solution
A voltage tracking circuit is implemented using PMOS transistors positioned in separate wells, which enhances ESD immunity and occupies less area by creating a stacked structure that directs ESD current effectively through parasitic diodes and transistors positioned in different wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If miniaturization is implemented to reduce device size, then device area is reduced, but ESD immunity deteriorates due to thinner dielectric thicknesses and lower breakdown voltages
Solution Approach 1:
The circuit is divided into multiple segments with transistors positioned in separate wells (first well, second well, third well). This segmentation allows ESD current to be distributed across multiple parasitic diodes and transistors, preventing any single point from bearing the full ESD stress while maintaining compact area.
Solution Approach 2:
Parasitic diodes and transistors positioned in different wells act as intermediaries to redirect and dissipate ESD current. These intermediary elements provide alternative current paths that protect the main circuit functionality from ESD damage while occupying minimal additional area.
2Reliability
If transistors are positioned in separate wells to enhance ESD immunity, then ESD protection is improved, but device area increases
Solution Approach 1:
The voltage tracking circuit is nested within a compact stacked structure where transistors in different wells are vertically or closely arranged. This nesting approach allows multiple ESD protection elements to coexist in a small footprint by utilizing three-dimensional space efficiency rather than spreading elements horizontally.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked structure by positioning transistors in separate wells that extend in the vertical dimension. This dimensional change allows ESD protection elements to be packed more densely, improving ESD immunity without proportionally increasing the planar device area.
3Area of moving object
If dielectric thickness is reduced for miniaturization, then device area is reduced, but dielectric breakdown voltage decreases leading to higher ESD susceptibility
Solution Approach 1:
Parasitic diodes and transistors are pre-positioned in separate wells to create ready-made ESD current paths before ESD events occur. This preliminary arrangement ensures that when ESD strikes, the current is immediately redirected through these pre-positioned protective elements rather than forcing current through the thin dielectric layers, preventing breakdown.
Solution Approach 2:
The parasitic elements that would normally be considered unwanted byproducts of the transistor structure are converted into beneficial ESD protection mechanisms. These parasitic diodes and transistors, inherent to the transistor fabrication process, are strategically positioned to serve as ESD current paths, turning a potential liability into an asset for ESD immunity.
Data Source
AI summary
A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.