Separated Data Paths for High-Speed Semiconductor Transfers
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Solution Overview
Problem
The data transfer speed of semiconductor devices is limited by complex logic circuits, which slow down data transfer and increase transferring time.
Innovation Solution
The implementation of separate logic circuits and interfaces for lower-speed-type data (e.g., SDR) and higher-speed-type data (e.g., DDR) within an integrated circuit, along with a driving circuit that manages data output based on the type of data received.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex logic circuits are used in semiconductor devices, then functionality and versatility are improved, but data transfer speed decreases and transferring time increases
Solution Approach 1:
The patent divides the semiconductor device into separate first and second data paths. The first data path is dedicated to higher-speed-type data (e.g., DDR) while the second data path handles lower-speed-type data (e.g., SDR). This segmentation allows each path to be optimized for its specific speed requirement, enabling the higher-speed path to operate at maximum performance without being constrained by the complexity requirements of lower-speed operations.
2Adaptability or versatility
If complex logic circuits are used in semiconductor devices, then functionality is improved, but transferring time increases
Solution Approach 1:
The patent segments the data transfer architecture into dedicated first and second data paths. The first data path is optimized for higher-speed-type data with reduced logic circuit complexity, while the second data path handles lower-speed-type data with full functionality. This segmentation reduces the transferring time for higher-speed data by eliminating unnecessary logical operations and components that would otherwise be required to support lower-speed operations.
Solution Approach 2:
The patent applies local quality by providing different levels of logic circuit complexity in different parts of the system. The first data path for higher-speed-type data has simplified logic circuits with fewer components, while the second data path for lower-speed-type data has more complex logic circuits. This localized optimization ensures that time-critical high-speed operations have minimal delay while lower-speed operations maintain full functionality.
3Speed
If separate logic circuits for lower-speed-type data and higher-speed-type data are implemented, then data transfer speed for higher-speed-type data is improved, but device complexity increases
Solution Approach 1:
The patent implements a driving circuit with driving subcircuits that can operate in different modes to support both higher-speed-type and lower-speed-type data transfers. The driving circuit includes multiple driving subcircuits that can be selectively activated based on the data type being transferred. This multi-functionality allows the driving circuit to serve both high-speed and low-speed data paths, reducing the need for completely separate driving circuits and thereby minimizing the increase in device complexity.
Data Source
AI summary
Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.