Separated Data Paths for High-Speed Semiconductor Transfers
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Solution Overview
Problem
The data transfer speed in semiconductor devices is limited by complex logic circuits, which can decrease the speed and lengthen the transferring time, particularly in memory devices.
Innovation Solution
Separate logic circuits for lower-speed-type and higher-speed-type data, such as SDR and DDR data, into distinct data paths with dedicated driving circuits to enhance data transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex logic circuits are used in semiconductor devices, then functionality and versatility are improved, but data transfer speed decreases and transfer time lengthens
Solution Approach 1:
The patent segments the data transfer system into multiple dedicated data paths (first data path for higher-speed-type data, second data path for lower-speed-type data) with separate logic circuits and driving circuits. This segmentation allows each path to be optimized for its specific speed requirement, resolving the contradiction between functionality and data transfer speed by enabling simultaneous operation of different speed modes without mutual interference.
2Adaptability or versatility
If complex logic circuits are used in semiconductor devices, then functionality is improved, but transfer time increases
Solution Approach 1:
The patent divides the data transfer architecture into separate dedicated paths for different speed types, each with its own logic circuit and driving circuit. This segmentation eliminates the time penalty associated with complex logic circuits by allowing higher-speed data transfers to occur through the first data path without being blocked or delayed by lower-speed operations in the second data path.
Solution Approach 2:
The patent implements a selection mechanism that preliminarily determines which data path to use based on the type of data transfer required. By pre-configuring the appropriate data path before the transfer begins, the system avoids the time loss that would occur if it had to dynamically switch between shared resources during the transfer process.
3Speed
If separate data paths for different speed types are implemented, then data transfer speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the device into modular dedicated data paths, where each path contains its own logic circuit and driving circuit. While this segmentation increases the total number of components, it organizes the complexity in a structured manner that allows for independent optimization and maintenance of each path, making the overall complexity manageable despite the increased component count.
Solution Approach 2:
The patent implements a selection mechanism that provides universal access to both data paths, allowing the device to handle multiple types of data transfers (higher-speed-type and lower-speed-type) through a unified interface. This multi-functionality approach manages device complexity by providing a single point of control that can direct traffic to the appropriate dedicated path based on the transfer requirements.
Data Source
AI summary
Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, a method includes: selecting a first interface to receive higher-speed-type data at a first clock frequency; transferring the higher-speed-type data with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit; outputting the higher-speed-type data by the driving circuit; selecting a second interface to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency; transferring the lower-speed-type data with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit, the first speed being higher than the second speed; and outputting the lower-speed-type data by the driving circuit.