Separated FinFET and GAA Cell Layout for Oxidation Mismatch Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The integration of different multi-gate devices, such as FinFETs and GAA transistors, on a single integrated circuit is challenging due to dimensional differences, leading to processing issues like oxidation mismatches between Nanowire and Nanosheet devices.

Innovation Solution

A semiconductor device layout is proposed that combines Nanowire, Nanosheet, and FinFET transistors, with specific layout options and isolation structures to mitigate manufacturing challenges, allowing for optimal integration and performance optimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If different multi-gate devices (FinFETs, Nanowire, Nanosheet transistors) are integrated on one integrated circuit, then design flexibility for speed and power optimization is improved, but manufacturing complexity and processing precision deteriorate due to dimensional differences and oxidation mismatches

Engineering Contradiction:

Improvedesign flexibilityVSAvoidprocessing precision

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The integrated circuit is divided into separate regions: a first region for FinFET devices and a second region for GAA devices (Nanowire and/or Nanosheet transistors). This spatial segmentation allows each device type to be manufactured with its own optimized process parameters, particularly for oxidation steps, while still achieving multi-gate device integration on a single IC for enhanced design flexibility.

Inventive Principle:

Principle #1Segmentation

2Reliability

If FinFETs and GAA transistors are integrated together, then gate control and leakage reduction are improved, but device complexity and integration difficulty increase

Engineering Contradiction:

Improvegate controlVSAvoidintegration difficulty

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Different device structures (FinFETs in the first region, GAA transistors in the second region) are implemented in different locations on the substrate. Each region maintains its locally optimized structure for maximum gate control effectiveness, while the overall integration complexity is managed through regional differentiation rather than uniform complex structures across the entire circuit.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12199100B2Multi-gate device integration with separated fin-like field effect transistor cells and gate-all-around transistor cells

Publication Date: 2025.01.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.