Sequence Checking Circuit for CAPHY Signal Path Testability
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Solution Overview
Problem
The command/address physical layer (CAPHY) in semiconductor chips lacks receiver terminals, making design for testability (DFT) challenging, as it does not have a data loopback mechanism like the data quadword physical layer (DQPHY), necessitating an improved design to ensure proper testing.
Innovation Solution
A semiconductor chip with a physical layer and processing circuit, incorporating a sequence checking circuit that includes a shift register circuit and output terminal logic gate to generate test result signals based on clock and data signals, allowing for the determination of signal transmission path operation status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the command/address physical layer is designed without receiver terminals to simplify the physical layer structure, then the physical layer design is simplified, but the design for testability deteriorates because no data loopback mechanism exists for testing
Solution Approach 1:
The invention segments the testing function from the main data transmission path by introducing a separate test mode. In normal operation, the physical layer maintains its simple transmitter-only design. For testing, a test mode is activated that enables receiver terminal functionality and data loopback capability, allowing comprehensive testing without affecting the simplified normal operation structure.
Solution Approach 2:
The receiver terminal and data loopback mechanism are designed to be dynamically activatable only during test operations. The physical layer can switch between a simple transmitter configuration during normal operation and a full-duplex configuration with receiver terminals enabled during testing, thus maintaining structural simplicity while providing testability when needed.
2Reliability
If a data loopback mechanism is added to enable testing of the command/address physical layer, then testability is improved, but the physical layer structure becomes more complex
Solution Approach 1:
The testing functionality is extracted as a separate, independently controllable feature. The data loopback mechanism and receiver terminal are not permanently integrated into the normal data path but are instead activated only when test operations are required. This extraction allows the physical layer to maintain its simple transmitter-only design during normal operation while providing comprehensive testing capabilities when needed.
Solution Approach 2:
A test mode control mechanism acts as an intermediary between the simple transmitter design and the testing requirements. This intermediary enables the physical layer to switch between operational modes, activating receiver terminals and data loopback paths only during testing, thus mediating between structural simplicity and testability without permanently complicating the design.
3Measurement precision
If the shift register circuit checks each data value multiple times to ensure accurate detection, then measurement precision is improved, but the checking time increases
Solution Approach 1:
The shift register circuit performs checking operations periodically at each clock cycle rather than continuously or with redundant checks. Each data value is checked exactly once when it passes through the shift register, with the checking occurring at regular periodic intervals synchronized to the clock signal. This periodic checking ensures accurate detection without unnecessary time consumption from repeated checks of the same data.
Solution Approach 2:
The shift register circuit is designed to automatically check each data value as it passes through, without requiring external verification or repeated checking. The inherent structure of the shift register enables self-checking functionality where each flip-flop naturally compares its state with the expected value at each clock cycle, providing accurate detection in a single pass through the register.
Data Source
AI summary
A semiconductor chip includes a physical layer and a processing circuit. The physical layer includes an input/output circuit, at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal transmitted through the input/output circuit and at least one test data signal transmitted through the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is configured to determine an operation status of the at least one signal transmission path according to a voltage level of the at least one test result signal.