Sequence Circuit Glitch Prevention and Power Reduction
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Solution Overview
Problem
Conventional clock gating techniques reduce power consumption in logic circuits but fail to suppress power consumption in clock signal generators, and existing glitch elimination circuits are prone to noise-induced abnormal operations, leading to irrelevant outputs and potential out-of-control states.
Innovation Solution
A sequence circuit with a detector, acceptor, inhibitor, clock pulse generator, determiner, and latch is introduced, which detects events in input signals, generates clock pulses based on specific timing, and inhibits further events to reduce power consumption and prevent glitches, while a logic circuit with combinational logic and a selector ensures accurate state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If glitch elimination circuit is disposed in post-stage of output decoder, then glitch output can be prevented, but noise may affect the glitch elimination circuit and cause abnormal operation
Solution Approach 1:
The patent prevents glitches at their source by using the sequence circuit's inherent state transition detection and clocked output mechanism. The detector identifies valid state changes, and the clock pulse generator synchronizes output transitions, preventing invalid intermediate states (glitches) before they can propagate. This preliminary prevention approach eliminates the need for post-stage glitch elimination circuits that would be vulnerable to noise, thereby maintaining reliability.
Solution Approach 2:
The sequence circuit acts as an intermediary between the latch and the output decoder, filtering out invalid state transitions. The detector and clock pulse generator work together to mediate the output signal, allowing only valid state changes to pass through to the decoder. This intermediary function prevents glitches from reaching the output stage without requiring additional noise-vulnerable glitch elimination circuits.
2Object-generated harmful factors
If delay circuit and latch are added to logic circuit, then glitch output may be prevented, but power consumption increases and out-of-control state may occur
Solution Approach 1:
The sequence circuit performs multiple functions within a unified structure: state transition detection, clock signal generation, and controlled state output. The detector identifies state changes, the clock pulse generator provides synchronized timing, and the latch outputs only valid next states. This multi-functional integration prevents glitches without requiring separate delay circuits and additional latches that would increase power consumption and complexity.
Solution Approach 2:
The patent changes the operational parameters of the circuit by using event-driven clock signal generation instead of continuous clocking. The clock pulse generator produces clock signals only when state transitions are detected, changing the temporal parameters of circuit operation. This parameter change eliminates the need for continuous operation of delay circuits and additional latches, thereby reducing power consumption while maintaining glitch prevention.
Data Source
AI summary
A sequence circuit (1) includes a detector (2) that detects an occurrence of an event based on an input signal, an acceptor (4) that accepts the event whose occurrence has been detected by the detector, an inhibitor (4) that inhibits the acceptor from accepting another event for a first period using the acceptance of one event by the acceptor as a trigger, a clock pulse generator (3) that generates one or more clock pulses during a period after a second period shorter than the first period elapses from the start of the first period until the first period ends, a determiner (5) that determines a next state based on a current slate and the event accepted by the acceptor, and a latch (6) that latches the next state using the clock pulse. An output of the latch is the current state.