Sequence Detection Circuit Using Divisibility Checks With Less Memory
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Solution Overview
Problem
Sequence detectors require significant memory reserves to detect large bit sequences, leading to larger and more expensive circuitry.
Innovation Solution
A sequence detection apparatus and method that uses a memory with a storage capacity substantially smaller than the incoming bit stream, where circuitry overwrites a binary number with each incoming bit to determine if the resulting binary number is divisible by a predetermined integer, allowing for real-time detection with reduced memory needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If greater memory reserves are used to detect large bit sequences, then sequence detection capability is improved, but circuit size and cost increase
Solution Approach 1:
The patent divides the sequence detection problem into segments by processing bits in groups of k bits at a time rather than storing the entire sequence. The memory is segmented to store only k bits at a time, with the system processing the incoming bit stream in chunks and performing divisibility checks on each segment, thereby reducing overall memory requirements while maintaining detection capability.
Solution Approach 2:
The patent changes the parameter of memory storage capacity from storing the entire sequence of n bits to storing only k bits at a time, where k is much smaller than n. This parameter change is achieved by processing the bit stream in segments and using mathematical operations (divisibility by predetermined integers) to detect sequences without requiring full sequence storage in memory.
2Adaptability or versatility
If greater memory reserves are used to detect large bit sequences, then sequence detection capability is improved, but implementation cost increases
Solution Approach 1:
The patent segments the bit stream processing into manageable chunks of k bits, which reduces the memory capacity required and consequently lowers implementation cost. By processing sequences in segments and using divisibility checks, the system achieves sequence detection capability with smaller, less expensive memory components.
Solution Approach 2:
The patent changes the memory storage parameter from n bits (full sequence) to k bits (segment), where k << n. This parameter reduction directly translates to lower implementation cost while maintaining sequence detection capability through mathematical processing of the segmented data.
3Area of stationary object
If memory storage capacity is reduced, then circuit size is decreased, but sequence detection accuracy may be compromised
Solution Approach 1:
The patent uses feedback mechanisms where the result of each divisibility check feeds into the next processing stage. The system continuously monitors the remainder of division operations and uses this feedback to determine when a complete sequence has been detected, maintaining accuracy despite reduced memory capacity by leveraging the mathematical properties of the divisibility checks.
Solution Approach 2:
The patent changes the detection parameter from storing and analyzing the full sequence to analyzing the remainder of division operations. By transforming the detection problem into a modular arithmetic problem (checking divisibility by predetermined integers), the system maintains detection accuracy with reduced memory by focusing on the critical parameter (remainder) rather than the entire sequence.
Data Source
AI summary
An apparatus for performing sequence detection on a stream of incoming bits comprises a memory and circuitry coupled to the memory. The circuitry is operative, for each bit of the stream of incoming bits, to overwrite a first binary number presently stored in the memory with a second binary number, and to provide an output indicative of when the second binary number is equal to a predetermined value. The output indicative of when the second binary number is equal to the predetermined value is, in turn, indicative of when a binary number constructed by the stream of incoming bits is divisible by a prescribed integer.