Sequence Processing Unit for On-Chip Debugging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging and performance measurement in complex system-on-chips (SoCs) are challenging due to high operational frequency and limited real-time external visibility, as external logic analyzers and emulators have limited capabilities and rely on signal pinouts or delayed serialized transmission.
Innovation Solution
A sequence processing unit (SPU) is integrated on-chip within the data processing system, capable of accessing internal signals and controlling on-chip resources, including trace debug circuitry, to perform debug operations and performance monitoring by generating complex debug events and sequences based on input triggers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external logic analyzers are used to debug hardware and software, then debugging capability is provided, but real-time visibility is limited and capabilities are restricted due to reliance on signal pinouts or delayed serialized transmission
Solution Approach 1:
The patent introduces an intermediary trace buffer and sequence processing unit that sits between the SoC internal signals and external analysis tools. This intermediary captures internal signals in real-time and makes them available for external analysis without requiring direct external access to internal pins, thus resolving the contradiction between providing debugging capability and maintaining real-time visibility.
Solution Approach 2:
The patent creates a copy of internal signals by routing them through trace buffers and sequence processing units. Instead of directly accessing internal signals from external tools (which is not possible), the system creates replicated copies of these signals that can be analyzed externally in real-time, eliminating the time loss associated with delayed serialized transmission.
2Measurement precision
If emulators are used to debug hardware and software, then debugging capability is provided, but real-time performance measurement is limited as emulators only mimic characteristics of an SoC
Solution Approach 1:
The patent segments the debugging function into separate components: trace debug circuits that capture real signals, sequence processing units that process the trace data, and external analysis tools that interpret the information. This segmentation allows each component to specialize in real-time performance measurement without relying on emulators that only mimic SoC characteristics, thus improving reliability while maintaining debugging capability.
3Adaptability or versatility
If SoC complexity increases, then functionality is enhanced, but difficulty in debugging and measuring performance increases
Solution Approach 1:
The patent implements a universal sequence processing unit that can handle multiple types of trace signals and debug operations through a single integrated architecture. This multi-functional unit processes various internal signals from different SoC components, allowing the system to maintain enhanced functionality while simplifying the debugging process through a unified approach rather than requiring separate solutions for each component.
Data Source
AI summary
A system includes one or more processors; one or more trace debug circuits configured to monitor one or more of instruction, data, and watchpoint buses of the one or more processors, and record information determined from said monitoring; and a sequence processing unit configured to provide a control signal to a trace debug circuit of the one or more trace debug circuits, wherein in response to the control signal, the trace debug circuit controls one or more of said monitoring and recording, and a system on a chip comprises the one or more processors, the one or more trace debug circuits, and the sequence processing unit.