Sequence Pattern Timing Control for Multi-Lane Skew Testing

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Solution Overview

Problem

Existing sequence pattern transmitters cannot control the skew between lanes of a plurality of lanes within the allowable range in high-speed serial bus systems like PCIe and USB, leading to ineffective skew resistance tests.

Innovation Solution

A sequence pattern generation device that synchronizes the start of data signal outputs across multiple modules, aligns the phases of clocks, and controls the transmission start timing to manage skew between lanes by adjusting delay amounts and clock phases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the sequence pattern transmitter uses conventional synchronization method, then the transmission can be initiated, but the skew between lanes cannot be controlled within the allowable range

Engineering Contradiction:
Improveskew control precisionVSAvoidtiming control mechanism
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing phase alignment of clock signals from multiple lanes before initiating the sequence pattern transmission. The control unit aligns the phases of clocks from all modules in advance, ensuring that the transmission start timing of each lane is pre-coordinated to meet the allowable skew requirements defined in PCIe standards.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using a control unit that monitors the phase relationships between clocks from different modules and dynamically adjusts the transmission start timing of each lane. This closed-loop control ensures that the skew between lanes remains within the allowable range by continuously comparing actual timing with target timing and making corrective adjustments.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If multiple lanes are transmitted simultaneously without skew control, then the transmission throughput is maximized, but the phase deviation exceeds the allowable skew range

Engineering Contradiction:
Improvephase alignment precisionVSAvoidtransmission throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies dynamics by making the transmission start timing of each lane adjustable and controllable rather than fixed. The control unit can dynamically set different delay amounts for each lane based on their phase relationships, allowing the system to adaptively optimize both phase alignment precision and transmission throughput by finding the optimal timing configuration.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If the transmission start timing is synchronized across all lanes, then the skew is minimized, but the ability to perform skew resistance tests is lost

Engineering Contradiction:
Improvetest capabilityVSAvoidskew control accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by making the transmission start timing adjustable rather than fixed. The control unit can dynamically change the timing configuration to match different test requirements, allowing the system to switch between synchronized transmission for normal operation and controlled skew transmission for skew resistance testing, thereby achieving both test capability and skew control accuracy.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12615039B2Sequence pattern generation device and transmission start timing control method thereof
Publication Date: 2026.04.28 ANRITSU CORP
  • US12615039B2 patent drawing
  • US12615039B2 patent drawing
  • US12615039B2 patent drawing

AI summary

A sequence pattern generation device that can control skew between lanes of a plurality of lanes by controlling a transmission start timing of a sequence pattern of a plurality of outputs. The sequence pattern generation device includes a primary module 2 and a secondary module 3 each having two outputs of data signals, and a device control unit 16 that, in a case where a start of a sequence of the outputs of the data signals is synchronized, sets delay amounts, aligns phases of clocks of the primary module 2 and the secondary module 3, locks phases of clocks of a primary data generation unit 26 of the primary module 2 and a secondary data generation unit 36 of the secondary module 3, and starts the sequence with the delay amounts set in the primary data generation unit 26 and the secondary data generation unit 36.