Sequencer Chaining Circuitry for Precise Multi-Channel Power Sequencing

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Solution Overview

Problem

Conventional sequencers have a limited number of output channels, making it difficult to sequence multiple components in electronic systems that require more channels, especially in power sequencing where strict timing is necessary, and there is no direct way to sequence continuously from one sequencer to another.

Innovation Solution

The implementation of sequencer chaining circuitry that connects separate sequencers in a feed-forward and/or feed-backward manner to ensure proper timing during sequencing, allowing for the scaling of sequencer output requirements and enabling continuous sequencing in both forward and reverse orders.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple separate sequencers are employed to provide required quantity of output channels, then the number of output channels is increased, but continuous sequencing with strict timing requirements cannot be maintained

Engineering Contradiction:
Improvenumber of output channelsVSAvoidtiming precision
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Multiple sequencers are merged into a single integrated sequencer device that provides a large number of output channels (e.g., 16 channels) while maintaining strict timing control. This combining approach eliminates the timing discontinuities that occur when multiple separate sequencers are used independently, thereby resolving the contradiction between increasing channel quantity and maintaining timing precision.

Inventive Principle:
Principle #5Merging (Combining)

2Device complexity

If conventional sequencers with limited output channels are used, then device complexity is reduced, but the ability to sequence multiple components is insufficient

Engineering Contradiction:
Improvesequencer structureVSAvoidnumber of sequenceable components
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The sequencer is designed as a universal device that can sequence multiple components (up to 16 or more output channels) while maintaining a relatively simple internal structure. The sequencer can be configured to control different types of components (memory devices, processors, I/O devices) through its multiple output channels, thereby achieving high adaptability without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If separate sequencers are used without chaining circuitry, then ease of manufacture is improved, but direct continuous sequencing between sequencers is not possible

Engineering Contradiction:
Improvesequencer assemblyVSAvoidcontinuous sequencing capability
Core Design Contradiction:
Ease of manufactureVSEase of operation

Solution Approach 1:

Chaining circuitry is introduced as an intermediary component that connects multiple sequencers together, enabling continuous sequencing operations across the chained sequence. The chaining circuitry receives timing signals from one sequencer and transmits them to the next, thereby facilitating seamless continuous sequencing while allowing each sequencer to remain a relatively simple, easily manufacturable unit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11544203B2Sequencer chaining circuitry
Publication Date: 2023.01.03 MICRON TECHNOLOGY INC
  • US11544203B2 patent drawing
  • US11544203B2 patent drawing
  • US11544203B2 patent drawing

AI summary

A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.