Sequential Charge Storage Pixels for Faster Charge Readout
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Solution Overview
Problem
Integrated devices for massively-parallel sample analysis are limited by their large size, portability issues, need for skilled operation, high power consumption, and cost, making them unsuitable for point-of-care applications, and they face challenges in efficiently collecting and reading out charge carriers due to limitations in charge transfer rates and readout processes.
Innovation Solution
The integration of multiple charge storage regions within an integrated circuit, allowing for simultaneous or sequential transfer and readout of charge carriers, which enhances the frequency and efficiency of charge collection and readout, and the use of intrinsic electric fields to improve charge transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple charge storage regions are integrated within an integrated circuit, then charge collection and readout efficiency is improved, but device complexity increases
Solution Approach 1:
The photodetector is divided into multiple charge storage regions (first charge storage region and second charge storage region) that are spatially separated and can operate independently. This segmentation allows simultaneous charge collection in one region while readout occurs from another region, improving overall efficiency without requiring complex temporal coordination
Solution Approach 2:
The patent introduces a spatial dimension to charge storage by creating multiple distinct regions (first and second charge storage regions) rather than using a single temporal sequence. This dimensional approach allows parallel operation of charge collection and readout functions, resolving the efficiency-complexity contradiction
2Speed
If charge carriers are transferred sequentially between multiple storage regions, then readout speed is improved, but power consumption increases
Solution Approach 1:
Charge carriers are pre-transferred to the second charge storage region during the charge collection phase, before readout is required. This preliminary action allows the readout process to proceed quickly without requiring high power during the critical readout period, as the charge is already positioned for rapid extraction
Solution Approach 2:
The system employs periodic charge transfer and readout cycles between the first and second charge storage regions. By alternating between charge collection in the first region and readout from the second region in periodic fashion, the system achieves high readout speed while managing power consumption through rhythmic, controlled operation rather than continuous high-power operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more frequent and efficient collection and readout of charge carriers, improving the performance of integrated devices for point-of-care applications by reducing size, increasing portability, and lowering power requirements while maintaining analysis efficiency.
Implementation Method 1
a photodetection region configured to generate charge carriers in response to receiving incident photons
Implementation Method 2
a second charge storage region electrically coupled to the first charge storage region and configured to induce, in a first direction away from the first charge storage region, a first intrinsic electric field
Data Source
AI summary
Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.