Sequential Chip Correlation Array for GNSS Acquisition
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Solution Overview
Problem
Conventional GNSS systems face challenges in achieving reduced Time to First Fix (TTFF) without increasing hardware gate count, which is critical for small form factor applications like hand-held devices, and struggle to handle weak signals and indoor/urban canyon conditions effectively for E911 compliance.
Innovation Solution
A GNSS baseband chip with a satellite signal acquisition module that simultaneously searches code shifts and frequency bins using a sequential chip correlation array with programmable signal generators, reducing hardware requirements and power consumption by sharing a sequential code mixer across M signal generators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple hardware blocks are used to acquire satellite signals from multiple satellites, then the acquisition capability is improved, but the silicon real estate and device size increase significantly
Solution Approach 1:
The patent combines multiple correlation operations into a single hardware block by sequentially processing different satellites' signals through the same correlator. The correlator is reconfigured for each satellite, sharing the same hardware resources across multiple acquisition tasks, thereby reducing the total number of hardware blocks needed while maintaining the capability to acquire signals from multiple satellites.
Solution Approach 2:
The patent employs dynamic reconfiguration of the correlator parameters (such as code phase, Doppler frequency) to adapt to different satellites. The same hardware block is dynamically adjusted to process signals from different satellites at different time intervals, enabling flexible multi-satellite acquisition without requiring dedicated static hardware for each satellite.
2Loss of time
If a larger number of correlators are provided to reduce TTFF, then the acquisition speed is improved, but the device size and power consumption increase drastically
Solution Approach 1:
The patent merges multiple correlator functions into a single shared correlator that operates sequentially. Instead of powering multiple correlators simultaneously, one correlator is reused across multiple time slots to process different satellites, dramatically reducing power consumption while achieving the same overall acquisition throughput through efficient time-division multiplexing.
Solution Approach 2:
The patent implements periodic reconfiguration and operation of the correlator for different satellites in a sequential manner. The correlator is activated, configured for a specific satellite, performs correlation, then deactivated or reconfigured for the next satellite, creating a periodic operation pattern that reduces average power consumption compared to continuous operation of multiple correlators.
3Speed
If multiple hardware blocks are used to perform parallel correlation, then the acquisition speed is improved, but the device complexity and gate count increase
Solution Approach 1:
The patent replaces static parallel hardware architecture with a dynamic sequential architecture. A single correlator is dynamically reconfigured to process different satellites in sequence, with control logic that manages the timing and parameter changes. This dynamic approach achieves similar acquisition throughput without the gate count overhead of multiple parallel correlator blocks.
Solution Approach 2:
The patent designs a universal correlator block that can perform correlation for any satellite by reconfiguring its parameters. This multi-functional correlator replaces multiple specialized correlators, each dedicated to a specific satellite. The universal correlator maintains acquisition speed by efficiently managing its operation across different targets while significantly reducing overall device complexity.
Data Source
AI summary
An arrangement of M signal generators in a global navigation satellite signal baseband chip for obtaining a sequential chip correlation array is provided. The sequential chip correlation array generates M×N code bit sequences, M in-phase and M quadrature-phase carrier mixed signals. The M signal generators are arranged consecutively. A programmable parameter is created for providing a spacing of TC between each N code bit sequences. A first carrier and code generator is provided within each signal generator for generating an in-phase and a quadrature-phase component of a first carrier signal, and N code bit sequences. The first carrier and code generators within adjacently arranged signal generators are programmed with same code chip offset, different carrier signal frequency, different code frequency, and different code phase offset. M in-phase and M quadrature-phase carrier mixed signals, and N code bit sequences are generated by the M signal generators based on the programmable parameter.