Sequential Circuit Topology for Increased Negative Setup Time
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Solution Overview
Problem
Current sequential circuits in semiconductor integrated circuits face challenges in achieving high operation speed and efficient scan test functions due to limitations in setup time and data transfer delays.
Innovation Solution
The proposed sequential circuit design includes a first gate circuit, a second gate circuit, and an output circuit that generate signals based on input signals, clock signals, and enable signals, utilizing NOR operations to create internal clock signals and control signal transitions, thereby increasing negative setup time and reducing data output delays, and incorporates a single stage of gate circuitry to enhance operation speed and support efficient scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential circuit design is used, then device complexity is reduced, but operation speed is limited due to insufficient negative setup time
Solution Approach 1:
The sequential circuit is divided into distinct functional blocks: a first gate circuit (NAND gate) for generating the first signal from input data and clock, a second gate circuit (NOR gate) for generating the internal clock signal, and an output circuit. This segmentation allows each block to be optimized independently, achieving negative setup time while maintaining manageable complexity through modular design.
Solution Approach 2:
The circuit employs dynamic signal generation where the internal clock signal is dynamically created by the NOR gate based on real-time conditions of the first signal and inverted clock input. This dynamic approach enables the circuit to adaptively achieve negative setup time, allowing input signal transitions to be reflected after the clock signal transitions, thereby increasing operation speed.
2Speed
If multiple stages of gate circuits are used, then logic functionality is enhanced, but data output delay increases
Solution Approach 1:
The design extracts only the essential gate circuits needed for the sequential circuit functionality, removing unnecessary intermediate stages. Specifically, the data transfer path uses minimal gating (one NAND gate for first signal generation) directly connected to the output circuit, eliminating redundant logic stages that would increase delay while preserving core logic functionality.
Solution Approach 2:
The circuit architecture allows signals to skip through optimized paths with minimal processing stages. The direct connection from the first gate circuit through the second gate circuit to the output circuit creates a streamlined data path that rushes signals through with minimal delay, achieving fast data transfer speed without compromising functionality.
3Reliability
If scan test path has same delay as normal path, then circuit simplicity is maintained, but scan test efficiency is reduced
Solution Approach 1:
The circuit implements different delay characteristics for different signal paths: the normal operational path is optimized for speed with minimal delay, while the scan test path is configured with longer delay. This local differentiation allows the scan test path to be specifically optimized for test efficiency without compromising the performance of the normal operational path, achieving reliable scan testing while maintaining overall circuit functionality.
Data Source
AI summary
A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.