Sequential Circuit Sensitization Using Directed Graph Topology
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Solution Overview
Problem
Existing techniques for sensitizing sequential circuits in complex systems-on-chips face challenges in accurately generating timing, power, and noise models due to difficulties in identifying and initializing internal memory nodes, leading to inaccuracies in characterizing circuit behavior.
Innovation Solution
A method involving the creation of a directed graph of the sequential circuit, topological sorting, and generating final vectors using only primary inputs to accurately replicate the circuit's behavior, ensuring accurate timing, power, and noise models are generated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If automated techniques trace the sequential circuit and identify internal memory nodes to generate stimuli, then sensitization can be performed automatically, but accuracy deteriorates due to difficulty in identifying all internal memory nodes and incorrect initialization
Solution Approach 1:
The patent creates a copy of the sequential circuit in the form of a directed graph structure that mirrors the circuit's topology. This graph copy allows automated analysis without directly manipulating the physical circuit, enabling accurate identification of all memory nodes through graph traversal algorithms while maintaining automation. The graph representation preserves the circuit's behavioral characteristics, allowing stimuli generation that accurately reflects actual circuit operation.
Solution Approach 2:
The patent introduces a directed graph as an intermediary representation between the physical sequential circuit and the sensitization process. This intermediary structure serves as a mediator that captures the circuit's topology and behavior, allowing automated tools to analyze and generate stimuli based on graph properties rather than directly interpreting complex circuit behavior. This intermediary layer resolves the contradiction by enabling automation while maintaining accuracy through the graph's faithful representation of the circuit.
2Ease of manufacture
If internal memory nodes are characterized as being driven by ideal voltage source, then simplification is achieved, but accuracy deteriorates because this is generally not the case in actual operation
Solution Approach 1:
The patent changes the characterization parameters from ideal voltage source assumptions to actual driver characteristics by analyzing the fanout of each memory node. Instead of using simplified ideal sources, the method determines the actual driving capability based on the number of loads connected to each node, creating a more accurate representation of real circuit behavior while maintaining automated analysis through graph-based parameter extraction.
3Extent of automation
If one or more internal nodes are not initialized to the values that would happen during actual operation, then automation is maintained, but accuracy deteriorates leading to incorrect timing and power values
Solution Approach 1:
The patent performs preliminary action by initializing all memory nodes to their actual operational values before conducting the sensitization analysis. Using the directed graph representation, the method traces back from outputs to identify all memory nodes and determines their correct initialization values based on the circuit's operational mode. This preliminary initialization ensures that subsequent automated analysis produces accurate timing and power values by starting from the correct operational state.
4Measurement precision
If the sequential circuit is broken up into strongly-connected components and characterized separately, then accuracy improves compared to manual techniques, but storage resources deteriorate due to significant storage requirements for waveforms and loadings
Solution Approach 1:
The patent extracts only the essential information needed for accurate characterization by focusing on the directed graph structure and memory node relationships. Instead of storing complete waveforms and loadings for each strongly-connected component, the method extracts critical topology information and initialization values from the graph representation. This extraction approach maintains accuracy by preserving the essential behavioral characteristics while dramatically reducing storage requirements by eliminating redundant waveform data.
Data Source
AI summary
A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a directed graph of the sequential circuit. Nodes of the graphs can be topologically sorted. In one embodiment, feedback loops in the directed graph can be removed before topologically sorting the nodes. Final vectors for the sequential circuit can be generated based on the sorted nodes. Notably, the final vectors are expressed only by primary inputs to the sequential circuit. Using only primary inputs in the final vectors accurately replicates the sequential circuit under test, thereby ensuring accurate timing, power, and noise arcs are measured.