Sequential Circuit Test Logic Using Configuration Register Readout
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Solution Overview
Problem
Existing integrated circuit devices lack a test logic circuit to check the states of electronic circuits, particularly in sequential circuits, which are difficult to test due to their dependence on internal states and the need for initialization, leading to increased error probability and maintenance challenges.
Innovation Solution
The integration of a test logic method that includes a main configuration register connected to an auxiliary test logic circuit, allowing control and observation of auxiliary inputs, decision blocks, and outputs in test mode, using existing logic gates to test sequential circuits without adding new logic, thereby maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test logic circuit is added to check states of electronic circuits, then test capability and fault detection are improved, but device complexity increases
Solution Approach 1:
The main configuration register is designed to serve dual purposes: storing configuration data during normal operation and controlling/observing test modes for sequential circuits. This multi-functionality allows the same hardware structure to support both operational and testing functions, improving test capability without proportionally increasing device complexity.
Solution Approach 2:
The test logic circuit utilizes existing logic gates and the main configuration register already present in the device, rather than requiring completely separate dedicated test hardware. The main configuration register controls the auxiliary test logic circuit, creating a self-contained testing system that leverages existing resources.
2Reliability
If new logic gates are added to test sequential circuits, then test coverage is improved, but power consumption increases
Solution Approach 1:
Existing logic gates in the sequential circuit are made multi-functional by enabling them to operate in both normal computational modes and test observation modes. The same logic gates that process data during operation are reused to observe and control test states, eliminating the need for additional dedicated test logic that would consume extra power.
Solution Approach 2:
The sequential circuit's existing logic infrastructure serves the dual purpose of both normal operation and self-testing. The main configuration register controls the auxiliary test logic circuit which utilizes the existing logic gates, allowing the circuit to test itself without requiring separate power-consuming test logic.
3Productivity
If test logic circuit is integrated into main device, then test efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The test logic circuit is merged with the main device structure by integrating the auxiliary test logic circuit with the main configuration register. This consolidation allows testing functionality to be built into the device fabric itself, improving test efficiency while avoiding the need for separate test hardware that would complicate manufacturing processes.
Data Source
AI summary
A test logic method (500) for an Integrated Circuit Device (100) including a main Integrated Circuit device (200) and an auxiliary Integrated Circuit device (300) having an auxiliary logical internal state (340). The method (500) includes a request (610), wherein a main configuration register (210) requests (610) testing (740) of an auxiliary logic circuit (330) via an auxiliary test logic circuit (350), testing (740), wherein the auxiliary test logic circuit (350) tests (740) the auxiliary logic circuit (330), displaying (750), wherein the auxiliary logic circuit (330) displays (750) the auxiliary logical internal state (340), and a reading (670), wherein the main configuration register (210) reads (670) the auxiliary logical internal state (340).