Two-Phase Sequential Circuit for Robust Timing Event Detection
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Solution Overview
Problem
Conventional timing event detection circuits in digital designs require pulse generators, delay chains, and dynamic logic gates, which are costly, unreliable, and inefficient, especially at low supply voltages and in deep sub-micron CMOS circuits, leading to over-design and increased power consumption.
Innovation Solution
A sequential circuit with a clocked comparator and digital logic block that detects timing events without the need for pulse generators or delay chains, using a two-phase clock signal to set and maintain a differential state, allowing for robust timing event detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TED circuits use pulse generators, delay chains, and dynamic logic gates, then timing event detection capability is achieved, but area overhead increases and reliability decreases
Solution Approach 1:
The invention extracts and eliminates the pulse generator and delay chain components from the conventional TED circuit, retaining only the essential timing event detection functionality through a simplified latch-based comparator approach that uses existing clock signals
Solution Approach 2:
The latch circuit serves multiple functions: it acts as both the timing event detector and the clocked element, eliminating the need for separate dedicated components and reducing overall circuit complexity while maintaining detection capability
2Use of energy by moving object
If conventional TED circuits operate at low supply voltages, then power consumption is reduced, but reliability and detection accuracy deteriorate
Solution Approach 1:
The invention changes the operating parameters by using level-sensitive latches instead of dynamic logic gates, which are inherently more robust at low voltages. The latch-based approach maintains stable operation and reliable timing event detection even when supply voltage is reduced, avoiding the noise and leakage issues that plague dynamic logic at low voltages
3Reliability
If worst-case timing constraints are used during logic synthesis, then circuit operation is guaranteed under all conditions, but power consumption and area increase due to over-design
Solution Approach 1:
The invention introduces dynamic timing event detection that adapts to actual runtime conditions rather than relying on static worst-case constraints. The TED circuit dynamically identifies actual timing violations only when they occur, allowing the rest of the system to operate with optimized, non-conservative timing parameters that reduce power and area
4Reliability
If delay line area is increased to ensure sufficient pulse width, then timing event detection coverage improves, but system performance and operation speed are limited
Solution Approach 1:
The invention removes the delay line component entirely from the TED circuit, replacing it with a latch-based approach that uses the existing clock signal phases. This eliminates the trade-off between delay line area and system performance, as the latch-based detector responds instantaneously to timing events without requiring artificial delay elements
Data Source
AI summary
A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.