Sequential Clock Controller Dynamic Bypass ATPG Power
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Solution Overview
Problem
Automatic test pattern generation (ATPG) in semiconductor devices leads to significantly higher power consumption during testing modes, causing false failures, damage to circuitry, and reliability issues due to increased junction temperatures, as well as inaccurate power estimation and excessive peak power requirements.
Innovation Solution
A controller system comprising a clock control unit and a bypass unit, configured to manage clock signals and sequential selection information, allowing only necessary clock controllers to operate during testing, thereby reducing power consumption and optimizing test patterns by dynamically bypassing unnecessary clock controllers in the chain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all clock controllers are activated during ATPG testing, then complete circuit coverage is achieved, but power consumption increases significantly (3-30 times higher than functioning modes)
Solution Approach 1:
The system dynamically configures clock controller activation based on test requirements. The bypass unit selectively activates or bypasses clock controllers during ATPG testing, allowing the system to adapt its power consumption profile to match actual testing needs while maintaining complete circuit coverage when necessary.
Solution Approach 2:
Different clock controllers are treated differently based on local test requirements. The bypass unit enables selective activation where only necessary clock domains are active during specific test phases, while others are bypassed to reduce power consumption locally without compromising overall test effectiveness.
2Productivity
If high power is supplied during testing modes, then comprehensive testing can be performed, but false failures and circuit damage occur due to excessive junction temperatures
Solution Approach 1:
The system dynamically adjusts power delivery to clock controllers based on real-time testing requirements. The bypass unit monitors test progress and selectively deactivates unnecessary clock controllers, preventing excessive temperature rise while maintaining testing productivity through adaptive power management.
Solution Approach 2:
The bypass unit allows the testing process to skip unnecessary clock controller activations. By bypassing clock controllers that are not required for the current test phase, the system rushes through the testing process efficiently without activating all power-consuming components, thereby avoiding thermal damage.
3Reliability
If a chain of N controllers is used for sequential testing, then comprehensive coverage is achieved, but test time increases due to sequential operation
Solution Approach 1:
The system dynamically reconfigures the controller chain during testing. The bypass unit enables parallel operation of selected clock controllers when test patterns allow, reducing sequential dependencies and minimizing test time while maintaining comprehensive coverage through adaptive test sequence management.
Data Source
AI summary
A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.