Sequential Cofactoring for Integrated Circuit Netlist Reduction
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Solution Overview
Problem
The synthesis and verification of state variable models in digital circuitry designs require significant computational resources, necessitating a method to reduce design size while preserving behavior for efficient logic synthesis and verification.
Innovation Solution
The implementation of sequential cofactoring, which involves analyzing the impact of specific gates by toggling their valuation at a particular time-step, generalizing combinational toggle analysis to enable more powerful reductions in sequential circuit designs. This is achieved by adding and manipulating circuitry to connect arbitrary gates to multiplexers and selector control circuitry, allowing for equivalent behavior assessment across all time-frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the design size is reduced to lower computational cost, then the computational resources required for synthesis and verification are reduced, but the behavior equivalence of the design must be preserved
Solution Approach 1:
The design is segmented by identifying and isolating specific gates for cofactoring analysis. The sequential circuit is divided into segments where individual gates can be analyzed independently through cofactoring, allowing computational resources to focus on critical portions rather than the entire design, thus improving efficiency while preserving overall behavior equivalence.
Solution Approach 2:
The invention changes parameters by introducing cofactoring variables that modify the valuation of specific gates at particular time-steps. By parameterizing the analysis around selected gates and their temporal behavior, the method enables targeted reduction of computational complexity while maintaining behavioral equivalence through systematic parameter exploration.
2Productivity
If combinational toggle analysis is used for gate impact assessment, then the analysis can be performed efficiently, but it cannot capture sequential behavior across multiple time-steps
Solution Approach 1:
The invention introduces dynamics by extending static combinational toggle analysis to sequential analysis that operates across multiple time-steps. The cofactoring approach dynamically evaluates gate impact at different time-points, allowing the analysis to adapt to temporal variations in circuit behavior while maintaining the efficiency benefits of combinational analysis methods.
Solution Approach 2:
The invention adds a temporal dimension to the analysis by incorporating time-step valuation into the cofactoring process. This transforms the analysis from a purely combinational, spatial evaluation to a sequential analysis that considers both spatial gate relationships and temporal behavior evolution, enabling comprehensive sequential analysis while preserving computational efficiency.
3Productivity
If sequential cofactoring is implemented by adding multiplexer circuitry, then more powerful design reductions can be achieved, but the circuit complexity increases
Solution Approach 1:
The multiplexer serves as an intermediary element that enables sequential cofactoring without permanently increasing circuit complexity. The multiplexer acts as a temporary control mechanism during analysis, allowing different gate valuations to be applied at different time-steps, and can be removed or optimized after the analysis is complete, thus enabling powerful reductions without permanent structural overhead.
Solution Approach 2:
The invention uses parameter changes by controlling multiplexer selection through time-step-dependent signals. Rather than permanently complexing the circuit structure, the method changes the operational parameters of the multiplexer based on temporal context, enabling sequential cofactoring effects while maintaining circuit simplicity through parameterized control rather than structural complexity.
Data Source
AI summary
Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.