Sequential Counting Status Circuits for NAND Flash Error Detection
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Solution Overview
Problem
Existing circuits for counting errors in page buffer output are either fast but inaccurate or accurate but slow, as they face challenges with current accuracy due to transistor mismatches and the need for binary search, which impacts detection efficiency during program and erase operations in NAND Flash arrays.
Innovation Solution
A detecting circuit comprising a series of counting status circuits and control logic that processes these circuits in a sequential order to determine the total number of error bits, using a fail bit detection unit (FBDU) to accurately and quickly count errors by incrementing the count upon successful detection of failed bits, thereby optimizing the counting process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a parallel circuit with current mirror is used to count errors simultaneously, then the detection speed is fast, but the measurement precision deteriorates due to transistor mismatches and current accuracy issues
Solution Approach 1:
The patent divides the error detection task into multiple sequential stages, where each stage processes a subset of error bits. This segmentation transforms the parallel inaccurate detection into a series of more precise sequential detections, improving overall measurement precision while maintaining acceptable detection speed through pipelined operation.
Solution Approach 2:
The patent employs periodic action by using multiple detection cycles with different reference current levels. Each cycle counts errors within a specific range, and by periodically varying the reference current and accumulating results across cycles, the system achieves high precision error counting without requiring perfectly matched transistors in a single parallel operation.
2Measurement precision
If a sequential counting method is used to improve accuracy, then the measurement precision is improved, but the productivity deteriorates due to increased timing overhead
Solution Approach 1:
The patent performs preliminary action by pre-charging node X to a known voltage level before each detection cycle and pre-calculating the reference current values for different error ranges. This preliminary preparation eliminates the need for complex real-time calculations during the actual counting process, maintaining high detection efficiency while achieving precise error counting through the subsequent sequential stages.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping the operation of multiple detection stages. While one stage is completing its counting operation, the next stage is already preparing its reference currents and control signals. This continuous pipeline operation minimizes idle time between stages, maintaining high productivity despite the sequential nature of the precise counting method.
Data Source
AI summary
Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.