Sequential Equivalence Checking for Circuit Design Verification
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Solution Overview
Problem
Current formal property verification systems require significant time and effort to re-verify properties for each modification in circuit design, leading to inefficiencies and the need for iterative design changes, as they lack support for iterative design methodologies and often result in false positives due to non-functional changes.
Innovation Solution
The method employs sequential equivalence checking to construct a composite circuit design by merging constraints and next-state functions from different versions, determining semantic equivalent states, and using these equivalences to automatically reconstruct proofs or provide counterexamples, thereby reducing the need for redundant verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal property verification is performed on each modified circuit design version, then verification completeness is improved, but verification time increases significantly
Solution Approach 1:
The system performs preliminary verification on the first circuit design version and stores the verification results. When a second version is created, the system retrieves and reuses these preliminary verification results instead of performing complete verification again, thereby reducing verification time while maintaining completeness through selective re-verification of only the modified portions.
Solution Approach 2:
The verification process is segmented into independent modules that can be selectively applied. The system identifies which portions of the circuit design have changed between versions and applies verification only to those segments, rather than verifying the entire design from scratch each time.
2Measurement precision
If complete re-verification is performed on modified circuit designs, then verification accuracy is improved, but false positives increase due to non-functional changes
Solution Approach 1:
The system applies different verification strategies to different parts of the circuit design based on their nature. Non-functional changes are identified and handled differently from functional changes, with the system focusing detailed verification only on functional modifications while dismissing or minimally processing non-functional changes, thereby reducing false positives while maintaining accuracy where needed.
3Reliability
If formal property verification is applied to every design modification, then design correctness is improved, but design iteration speed decreases
Solution Approach 1:
Verification results from preliminary design versions are stored and reused in subsequent iterations. This preliminary action of caching verification outcomes allows designers to iterate quickly on non-critical changes while maintaining correctness guarantees for functional modifications, thereby improving both design correctness and iteration speed.
4Productivity
If sequential equivalence checking is used to leverage previous verification results, then verification efficiency is improved, but system complexity increases
Solution Approach 1:
The system introduces a verification result cache and matching mechanism as an intermediary between the verification engine and the design database. This intermediary stores preliminary verification results and automatically matches them against new design versions, enabling efficient reuse of previous work without requiring complex changes to the core verification algorithm, thus improving efficiency while managing complexity through modular architecture.
Data Source
AI summary
A system and method for providing formal property verification across circuit design versions is described. In one embodiment, the system receives a first version and a second version of a circuit design. The received first version has a first set of constraints, a first set of next-state functions representing the first version of the circuit design, and a first property that has been verified as true for the first version of the circuit design. The received second version has a second set of constraints, a second set of next-state functions representing the second version of the circuit design, and a second property for the second version of the circuit design. The described embodiments further construct a composite circuit design based on the first set of constraints, the first set of next-state functions, and the first property and further based on the second set of constraints, the second set of next-state functions, and the second property. A third property is constructed for the composite circuit design in which the first property implies the second property. Some described embodiments output a proof or a counterexample for the second circuit design, based on the proof of the third property for the composite circuit design, since a user of the system and method is trying to verify the second circuit design, not the composite circuit design.