Sequential Equivalence Checking for Retimed IC Designs
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Solution Overview
Problem
Current techniques struggle to verify designs that are both globally retimed and sequentially optimized, as conventional sequential verification methods fail to effectively handle these complex transformations.
Innovation Solution
A system performs sequential equivalence checking by verifying conditional equivalence between sub-blocks and top-level designs, using integer linear programming to determine necessary register additions for temporal equivalence, allowing for hierarchical verification of large IC designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional sequential equivalence checking is used on retimed designs, then verification can be performed on designs without global transformations, but the method fails when designs are globally retimed because equivalence on retimed design sub-blocks is broken
Solution Approach 1:
The verification process is divided into two independent stages: temporal equivalence checking (which handles retiming transformations by comparing register counts on corresponding cycles) and logical equivalence checking (which verifies functional equivalence). This segmentation allows each stage to address specific aspects of equivalence without the other's complications, enabling reliable verification of globally retimed designs.
Solution Approach 2:
Temporal equivalence serves as an intermediary verification step between structural comparison and functional equivalence checking. By first establishing that the designs have equivalent temporal behavior (same number of registers on corresponding cycles), the system creates a foundation that enables subsequent logical equivalence checking to proceed reliably on retimed designs.
2Productivity
If sequential optimization techniques are applied to reduce design size and power consumption, then smaller and faster designs are achieved, but sequential equivalence checking becomes much harder due to large number of registers
Solution Approach 1:
The verification task is segmented into temporal equivalence checking (handling register count comparisons) and logical equivalence checking (handling functional verification). This division reduces the overall verification complexity by addressing the large register count issue in the temporal stage, allowing the logical stage to focus on functional equivalence with reduced burden.
Solution Approach 2:
The approach changes the verification parameters by introducing cycle-based temporal equivalence checking. Instead of directly tackling the full sequential equivalence problem on optimized designs with many registers, the method transforms the problem into comparing register counts on corresponding cycles, thereby managing verification complexity while maintaining effectiveness on optimized designs.
3Speed
If retiming is applied as a global transformation to move registers across combinational logic blocks, then design performance is improved, but conventional sequential verification techniques fail because they are restricted to local transformations
Solution Approach 1:
Verification is segmented into temporal equivalence checking that specifically handles global retiming transformations by comparing register counts on corresponding cycles, followed by logical equivalence checking. This segmentation enables the verification system to adapt to global transformations like retiming that conventional local-transformation-based methods cannot handle.
Solution Approach 2:
The two-stage verification approach serves multiple functions: it handles both locally and globally transformed designs, accommodates various optimization techniques, and provides a unified framework that works across different transformation types. This universality makes the verification technique adaptable to retimed designs while maintaining effectiveness for other transformations.
Data Source
AI summary
One embodiment of the present invention provides a system that performs sequential equivalence checking between integrated circuit (IC) designs. During operation, the system receives a first IC design and a second IC design. Each of the first and second IC designs includes a top design level and a bottom design level, and the bottom design levels include one or more sub-blocks within the corresponding top design levels. The system then verifies if each of the sub-blocks in the bottom design level of the first design is conditionally equivalent to a corresponding sub-block in the second design. Note that two designs are conditionally equivalent if the two designs can become sequentially equivalent by adding registers on the input and output ports of the two designs. The system additionally verifies if the top design level of the first design is conditionally equivalent to the top design level of the second design and if the first design is temporally equivalent to the second design.