Sequential Equivalency Fault Propagation Analysis
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Solution Overview
Problem
Current fault propagation analysis in safety-critical systems, such as automotive electronics, is inefficient due to the need for extensive simulation of various scenarios and manual identification of safe faults, which is labor-intensive, error-prone, and incomplete, especially when dealing with complex hardware safety mechanisms and millions of potential fault locations.
Innovation Solution
A method for performing a sequential equivalency check that minimizes circuit logic duplication by identifying registers where faults cannot or can propagate, using a combinatorial and sequential check to efficiently model fault propagation and detection, and displaying fault propagation paths within a waveform debugger.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive simulation of various fault scenarios is performed, then fault propagation analysis accuracy is improved, but computational time and resources increase significantly
Solution Approach 1:
The patent segments the circuit into distinct components and identifies specific fault locations, separating the analysis into manageable portions. By dividing the circuit into segments with identified fault locations, the method enables targeted analysis rather than exhaustive simulation of all possible fault scenarios, thereby maintaining accuracy while reducing computational time.
Solution Approach 2:
The patent performs preliminary identification of fault locations and safe faults before conducting full propagation analysis. By pre-identifying potential fault locations and using formal methods to determine safe faults in advance, the system reduces the scope of subsequent simulation efforts, achieving both high accuracy and efficient computational resource utilization.
2Measurement precision
If manual identification of safe faults is performed, then analysis completeness is improved, but labor intensity and error risk increase
Solution Approach 1:
The patent implements automated formal verification methods that enable the system to self-identify safe faults without manual intervention. The formal methods automatically analyze circuit properties and determine which faults are safe (cannot propagate to outputs) versus dangerous, eliminating the need for manual identification while maintaining complete and accurate analysis results.
Solution Approach 2:
The patent replaces manual mechanical analysis with automated formal verification methods. By substituting human expert analysis with computer-based formal methods, the system achieves both complete analysis coverage and elimination of manual labor, thereby improving analysis completeness while significantly reducing labor intensity and human error risk.
3Measurement precision
If formal verification is applied to all fault locations, then verification accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies formal verification selectively to specific fault locations rather than uniformly to all circuit elements. By identifying and focusing formal analysis on critical fault locations where verification is most needed, the method maintains high verification accuracy for dangerous faults while reducing computational complexity by avoiding redundant analysis of safe fault locations.
Solution Approach 2:
The patent performs partial formal verification by first identifying a subset of critical fault locations that require detailed analysis. Rather than applying exhaustive formal verification to all possible fault locations, the method applies formal methods to the necessary subset, achieving adequate verification accuracy while managing computational complexity through selective application.
Data Source
AI summary
A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.