Sequential Flip-Flop Control for Leakage Current Reduction
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Solution Overview
Problem
The increasing leakage current in deep-submicrometer CMOS circuits due to scaling down of transistors poses a significant challenge for power dissipation in electronic devices, particularly in sequential circuits, where existing methods like using multiplexers or memory to implement minimum leakage bits (MLBs) either consume significant area or power.
Innovation Solution
A system comprising combinational logic circuits, reset flip-flops, set-reset flip-flops, and a control module that resets and sets these flip-flops when the sequential circuit enters a standby mode, using a power management unit to forward a sleep signal, thereby reducing leakage current without the need for additional components or memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiplexers are added to feed MLBs to the combinational logic circuit during standby mode, then leakage current is reduced, but device area and timing overhead increase significantly
Solution Approach 1:
The patent extracts the leakage reduction function from complex external components (multiplexers and memory) and implements it directly within the existing flip-flop structures. By taking out the unnecessary MLB storage and routing infrastructure, the solution reduces leakage while minimizing area overhead, as only minimal modifications to the flip-flop reset and set mechanisms are required.
Solution Approach 2:
The flip-flops are modified to serve their own leakage reduction needs by incorporating direct reset and set mechanisms that can be activated during standby mode. The flip-flops themselves generate and apply the control signals needed to force minimum leakage states, eliminating the need for external multiplexers and memory components that would otherwise be required to manage MLB distribution.
2Loss of energy
If multiplexers are added to feed MLBs to the combinational logic circuit during standby mode, then leakage current is reduced, but timing overhead increases considerably
Solution Approach 1:
The patent implements preliminary action by pre-configuring the flip-flops with reset and set mechanisms that can instantly force minimum leakage states when standby mode is detected. The control logic is designed to recognize standby conditions and immediately activate the leakage reduction mechanism without requiring complex runtime decision-making or additional timing cycles, thus minimizing timing overhead while effectively reducing leakage.
Solution Approach 2:
Instead of using multiplexers to selectively route different inputs to the combinational logic circuit, the patent inverts the approach by directly controlling the flip-flop outputs to force minimum leakage states. This inversion eliminates the need for complex routing logic and timing coordination associated with multiplexer-based solutions, thereby reducing timing overhead while achieving the same leakage reduction goal.
3Area of stationary object
If memory is implemented to store MLBs for standby mode, then area overhead is reduced compared to multiplexers, but power consumption increases due to holding and moving MLBs
Solution Approach 1:
The patent extracts the MLB storage function from dedicated memory components and embeds it directly within the flip-flop structures. By taking out the separate memory infrastructure, the solution reduces area overhead while avoiding the dynamic power consumption associated with memory read/write operations. The flip-flops themselves serve as both functional elements and leakage state storage, eliminating redundant power-consuming operations.
Solution Approach 2:
The flip-flops are modified to self-manage their leakage states without requiring external memory support. The reset and set mechanisms allow the flip-flops to autonomously maintain minimum leakage states during standby mode, eliminating the need for power-consuming memory access operations. This self-service approach reduces both area and power consumption by consolidating storage and functional capabilities within the existing flip-flop structures.
Data Source
AI summary
A system and device for reducing leakage current in a sequential circuit is disclosed. In one embodiment, a system for reducing leakage current in a sequential circuit includes a combinational logic circuit, one or more reset flip-flops coupled to the combinational logic circuit, and one or more set-reset flip-flops coupled to the combinational logic circuit. The system further includes a control module coupled to the reset flip-flops and to the set flip-flops and configured to reset the reset flip-flops and to set the set-reset flip-flops when a standby mode of the sequential circuit is triggered.