Sequential-Hybrid Accumulator Layouts to Reduce CIM Routing Congestion
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Solution Overview
Problem
Traditional compute-in-memory (CIM) circuit designs face significant routing congestion due to complex and intertwined electrical connections, leading to inefficient use of metal layers, increased manufacturing costs, and reduced scalability.
Innovation Solution
Implementing a sequential or hybrid floor plan for CIM circuits that optimizes routing by reducing the number of metal layers through strategic placement of computing units, such as local and global accumulators, and employing a balanced approach of sequential and parallel routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional parallel floor plan is used for CIM circuits, then computing power and processing speed are improved, but routing congestion and metal layer usage increase significantly
Solution Approach 1:
The patent segments the computing units into different functional groups (e.g., MAC units, accumulators, selectors) and organizes them in a sequential pipeline architecture. This segmentation allows each segment to perform specific operations independently, reducing the need for complex interconnections while maintaining computing power through pipelined parallel processing.
Solution Approach 2:
The patent transitions from a two-dimensional parallel floor plan to a three-dimensional sequential-pipeline architecture by adding the time dimension through pipelining. Multiple computing stages operate at different clock cycles, enabling parallel computation to be achieved through sequential stages processed over time, thereby reducing spatial routing complexity.
2Productivity
If complex routing connections are implemented to achieve high computing power, then processing capability is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent implements local quality by providing different routing configurations for different regions of the circuit. Critical paths receive optimized routing resources while less critical connections use standard routing, allowing high processing capability in essential operations without uniformly increasing manufacturing complexity across the entire device.
Solution Approach 2:
The patent changes the routing parameter from fixed parallel connections to dynamic sequential-pipeline connections that can be configured based on computational requirements. This allows the same physical infrastructure to support varying processing capabilities by reconfiguring the activation sequence of pipeline stages, reducing manufacturing complexity.
3Quantity of substance
If more metal layers are used to accommodate complex routing, then routing capacity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent ensures continuity of useful action through the sequential pipeline architecture where computational results are continuously passed from one stage to the next without requiring complex lateral routing. This continuous flow through time reduces the need for additional metal layers to accommodate complex spatial routing patterns.
Solution Approach 2:
The patent applies preliminary action by pre-positioning computing units and their interconnections in a sequential pipeline layout during design, rather than attempting to optimize complex parallel connections after placement. This preliminary structuring of the architecture inherently reduces routing capacity requirements and metal layer complexity.
4Ease of manufacture
If sequential floor plan is used to reduce routing congestion, then manufacturing simplicity is improved, but computing power and processing speed decrease
Solution Approach 1:
The patent introduces dynamics by making the sequential pipeline stages activatable in different sequences based on computational requirements. While the physical layout is sequential and simple to manufacture, the system dynamically activates different pipeline stages at different clock cycles to achieve parallel processing throughput, thereby maintaining computing power despite the simplified sequential architecture.
Data Source
AI summary
A memory device may comprise a memory array, a first computing unit, and a second computing unit. The memory array may comprise a plurality of memory cells to store weights for a neural network. The first computing unit can be configured to receive the stored weights from the plurality of memory cells, and to generate a first partial sum according to the stored weights. The second computing unit can be configured to receive the stored weights from the plurality of memory cells and the first partial sum, and to generate a second partial sum according to the stored weights and the first partial sum. The second computing unit can be sequentially coupled to the first computing unit.