Sequential Latch Circuit for Diagnostic Hold Timing Compliance
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Solution Overview
Problem
Sequential storage circuits in data processing circuits face hold timing violations when operating in diagnostic mode due to variations in clock signals, leading to old data being captured instead of new data, particularly on diagnostic data paths without combinational logic, which existing solutions address with buffers or lock-up latches but at the cost of increased circuit area or external clock balancing.
Innovation Solution
A latching device with an additional oppositely clocked latching element that introduces a half clock cycle delay for diagnostic data, ensuring that new data is captured by synchronizing the clock signals for input and output latching elements, thereby preventing hold timing violations without significantly increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are added to the diagnostic data path to introduce delay, then hold timing violations are prevented, but circuit area increases significantly
Solution Approach 1:
The patent merges the diagnostic data path latch with the operational data path latch structure by using the same master and slave latches for both purposes. The scan input is integrated into the existing latch architecture, allowing diagnostic and operational functions to share the same physical components, thereby avoiding additional area overhead for separate diagnostic buffers.
Solution Approach 2:
The master and slave latches serve dual functions: they handle both operational data transmission and diagnostic data scanning. The same latch elements are used for both purposes by controlling their transparency through clock signals, eliminating the need for dedicated diagnostic buffer elements and reducing overall circuit area.
2Reliability
If lock-up latches are inserted between the two latches to introduce delay, then hold timing violations are prevented, but device complexity increases due to external separate clocked elements and clock balancing requirements
Solution Approach 1:
The patent combines the diagnostic delay function with the existing operational latch structure. The scan latch uses the same master and slave elements as the operational path, integrating the delay function into the existing architecture rather than adding separate external elements, thereby reducing device complexity.
Solution Approach 2:
The same latch elements perform both operational data latching and diagnostic data scanning functions. By controlling the transparency of these universal elements through clock signals, the patent eliminates the need for separate lock-up latches and external clock balancing circuits, simplifying the overall device structure.
3Speed
If the diagnostic data path is made direct without combinational logic, then diagnostic speed is improved, but hold timing violations occur when clocks are not perfectly aligned
Solution Approach 1:
The patent uses periodic clock signals to control the transparency of the master and slave latches in a cyclic manner. During the first phase of the clock cycle, the master latch is transparent to capture diagnostic data. During the second phase, the slave latch becomes transparent to transfer the data. This periodic action ensures that data is captured and transferred at the correct timing intervals, preventing hold violations while maintaining fast diagnostic throughput.
Solution Approach 2:
The master latch captures the diagnostic data value during the first phase of the clock cycle before the slave latch becomes transparent. This preliminary capture ensures that the data is stable and ready for transfer, preventing the slave latch from capturing old data values and ensuring accurate data capture even with clock skew.
Data Source
AI summary
A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode.