Sequential LDPC Decoding for OFDM Link Latency

The patent combines multiple coding and decoding engines into a single integrated engine that processes bits sequentially according to their significance. Instead of implementing separate coding/decoding paths for different bit groups, the invention merges them into one unified processor that handles least significant bits first with full error correction, then proceeds to more significant bits, thereby reducing device complexity while maintaining error correction capability.

The patent segments the error correction process by bit significance rather than by separate coding engines. The single decoding engine processes bits in sequential segments starting from least significant to most significant, applying appropriate error correction strategies to each segment. This segmentation approach maintains the benefits of multilevel coding while avoiding the complexity of multiple parallel engines.

The patent implements continuous processing within a single decoding engine that seamlessly transitions from decoding least significant bits to more significant bits without interruption. The useful action of error correction continues uninterrupted through all bit groups, eliminating the latency introduced by multiple sequential processing stages. The decoder maintains continuous operation, processing bits in real-time as they become available.

The patent performs preliminary decoding of less significant bits first, which provides information that aids in the subsequent decoding of more significant bits. This preliminary action establishes a foundation that speeds up the overall decoding process, as the single engine can use results from earlier bit groups to inform decisions about later groups, reducing total latency compared to waiting for all bits to be processed equally.

The patent implements dynamic modulation selection that adapts to actual channel conditions in real-time. Rather than using fixed cautious thresholds, the system continuously monitors decoding performance and signal quality, dynamically adjusting the modulation scheme to maximize capacity while maintaining reliability. This dynamic approach allows the system to exploit favorable channel conditions more aggressively, increasing link capacity without sacrificing reliability.

The patent employs feedback mechanisms where decoding results and signal quality metrics are fed back to the modulation selection process. The single decoding engine provides performance feedback that informs whether the current modulation scheme is appropriate, allowing the system to confidently select higher-order modulations when conditions permit. This feedback loop replaces cautious prediction with evidence-based decisions, improving both reliability and capacity.