Configurable Clock Skews for Time Borrowing in Sequential Logic
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Solution Overview
Problem
Conventional time borrowing schemes in integrated circuits face limitations in achieving optimal performance due to limited clock delays, complexity, and issues with race conditions and clock timing, particularly in accommodating the delays of slow logic paths without slowing down the entire circuit.
Innovation Solution
The implementation of a programmable integrated circuit with multiple clock distribution networks and programmable routing and delay circuitry allows for intelligent placement of clock sources and adjustment of clock skews, enabling time borrowing by distributing clock signals through global, regional, and peripheral networks, thereby optimizing circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional flip-flop-based sequential logic circuits are used with regular clock distribution, then ease of circuit design is improved, but circuit performance is limited due to clock speed being slowed to accommodate worst-case delays
Solution Approach 1:
The patent divides the clock distribution system into multiple types of clock networks (global, regional, peripheral) with different distribution scopes and characteristics. This segmentation allows different parts of the circuit to receive appropriately timed clock signals, enabling faster overall circuit performance while maintaining design regularity through structured clock distribution.
Solution Approach 2:
The patent applies different clock distribution strategies to different regions of the circuit. Local clock networks provide customized clock timing to specific areas with unique timing requirements, allowing fast logic paths to operate at higher speeds without being constrained by worst-case delays in other parts of the circuit.
2Productivity
If conventional time borrowing schemes with limited clock delays are used, then some performance improvement is achieved, but optimal performance cannot be obtained due to limited number of delays available
Solution Approach 1:
The patent introduces programmable routing and delay circuitry that allows dynamic adjustment of clock skew values. This enables the system to adapt clock timing to match the specific timing requirements of different logic paths, providing optimal performance for varying circuit configurations rather than being constrained to fixed delay values.
Solution Approach 2:
The patent changes the clock skew parameter dynamically through programmable delay circuitry. By adjusting the skew value to match the difference in propagation delays between fast and slow logic paths, the system can optimize performance for different operating conditions and circuit configurations.
3Reliability
If fixed time borrowing flip-flops are used, then a fixed amount of time borrowing is provided, but optimal performance cannot be achieved and the scheme is prone to race conditions and clock timing issues
Solution Approach 1:
The patent replaces fixed time borrowing mechanisms with dynamic, programmable clock skew adjustment. This allows the system to adaptively set clock timing to prevent race conditions while maximizing performance, rather than being constrained by fixed borrowing amounts that may cause timing violations in certain configurations.
Data Source
AI summary
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.