Sequential Logic Element Performance Check via Simulation Waveforms
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Solution Overview
Problem
In the design process of fully-customized integrated circuits, determining characteristic parameters of sequential logic elements, such as setup time and hold time, is difficult and typically requires manual checks, which are time-consuming and labor-intensive, degrading the efficiency of the design process.
Innovation Solution
A method and apparatus for determining the performance of sequential logic elements by obtaining a performance check file, simulating the circuit using simulation waveforms, and adjusting input signals to identify and correct timing errors, thereby automating the process and improving accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual check is used to determine characteristic parameters of sequential logic elements, then accuracy can be maintained, but time consumption and labor intensity increase significantly
Solution Approach 1:
The patent replaces manual mechanical checking with automated simulation-based verification. A simulation waveform is automatically generated and applied to the sequential logic element, and the characteristic parameters (setup time, hold time) are extracted through automated analysis of simulation results, eliminating manual intervention while maintaining accuracy
Solution Approach 2:
The system performs self-verification by automatically generating simulation waveforms, executing simulations, and extracting characteristic parameters without external manual input. The sequential logic element's performance is self-tested through the automated simulation process, reducing labor intensity while preserving measurement accuracy
2Measurement precision
If manual check is used to determine characteristic parameters of sequential logic elements, then detailed analysis can be performed, but design efficiency deteriorates
Solution Approach 1:
Manual analysis is replaced with automated simulation and parameter extraction. The system automatically generates simulation waveforms, executes the simulation, and extracts characteristic parameters through programmed analysis, maintaining detailed analysis capability while dramatically improving design efficiency
Solution Approach 2:
The patent changes the approach from manual parameter measurement to automated parameter extraction through simulation. By transforming the analysis method into a parameter-based simulation approach, detailed analysis is preserved while efficiency is enhanced through automation
3Loss of time
If automated simulation is used to determine characteristic parameters, then time consumption and labor are reduced, but implementation complexity increases
Solution Approach 1:
The automated verification process is segmented into distinct modules: simulation waveform generation, simulation execution, and parameter extraction. Each module handles a specific task, making the overall complex process manageable and maintainable through clear separation of concerns
Solution Approach 2:
The patent introduces a simulation waveform as an intermediary between the sequential logic element and the analysis process. This intermediary enables automated verification by providing a standardized interface for testing and parameter extraction, reducing implementation complexity
Data Source
AI summary
A method for determining performance of sequential logic elements includes the following operations. To check a circuit, a performance check file corresponding to each of the sequential logic elements of the circuit is obtained; and the circuit is separately simulated to obtain the simulation result, by using a plurality of simulation waveforms, based on the performance check file corresponding to each of the sequential logic elements. The performance check file may be used to determine, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result.


