Sequential Logic Circuit Polarity Optimization for Critical Paths

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Solution Overview

Problem

Existing logic circuit designs for clock synchronous sequential circuits often include redundant inverters that increase the number of gate stages, hindering the speed of logic operations due to the necessity of polarity matching inverters for positive logic inputs and outputs.

Innovation Solution

The method involves using a combination of sequential circuits with positive-logic and negative-logic input/output terminals to optimize the series path by replacing certain sequential circuits with others that have fewer gate stages, thereby deleting redundant inverters and reducing the number of gate stages in the critical path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If polarity matching inverters are added to sequential circuits with positive logic inputs and outputs, then the logic circuit can be standardized and easier to manufacture, but the number of gate stages increases and logic operation speed decreases

Engineering Contradiction:

Improvestandardization of logic circuitVSAvoidlogic operation speed

Core Design Contradiction:

Ease of manufactureVSSpeed

Solution Approach 1:

The patent changes the logic level parameter of sequential circuits from positive logic to negative logic. By using negative logic sequential circuits, the patent eliminates the need for polarity matching inverters while maintaining standardization, thus resolving the contradiction between ease of manufacture and logic operation speed

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent inverts the logic level from positive logic to negative logic. This inversion allows sequential circuits to directly connect with combinational circuits without requiring additional polarity matching inverters, thereby reducing gate stages and improving logic operation speed while maintaining circuit standardization

Inventive Principle:

Principle #13The other way round (Inversion)

2Speed

If the number of gate stages in sequential circuits is decreased, then logic operation speed improves, but the complexity of optimizing the critical path increases

Engineering Contradiction:

Improvelogic operation speedVSAvoidcomplexity of optimizing critical path

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent changes the logic level parameter to negative logic, which simplifies the critical path optimization process. By using negative logic sequential circuits, the patent reduces the number of gate stages and eliminates polarity matching inverters, making the optimization process more straightforward while improving logic operation speed

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8566763B2Logic circuit design method, logic design program, and semiconductor integrated circuit

Publication Date: 2013.10.22 RENESAS ELECTRONICS CORP

AI summary

A computer device which performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit performs optimization processing for decreasing the number of gate stages in a critical path between sequential circuits in the data path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal.