Sequential Logic Reset Using Emulated Asynchronous Signals
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Solution Overview
Problem
Existing synchronous logic circuits require additional gates to enable both synchronous and asynchronous reset, which increases area, power consumption, and complexity, especially in applications with many sequential logic elements.
Innovation Solution
The method involves generating a synchronous reset signal that is converted into an emulated asynchronous reset signal, allowing sequential logic to be synchronously reset without the need for separate logic at the data input of each element, thereby reducing the number of logic elements required for reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate synchronous and asynchronous reset logic is implemented for each sequential logic element, then both synchronous and asynchronous reset functions are achieved, but the number of logic elements increases, leading to increased area and power consumption
Solution Approach 1:
The patent combines synchronous and asynchronous reset logic into a single unified reset unit that serves all sequential logic elements. Instead of having separate reset circuits for each flip-flop, a centralized reset module generates both synchronous and asynchronous reset signals, reducing the overall number of logic elements and minimizing circuit area while maintaining full reset functionality.
Solution Approach 2:
The unified reset unit is designed to perform multiple functions: it generates both synchronous and asynchronous reset signals, controls multiple sequential logic elements simultaneously, and can operate in different reset modes. This multi-functional design eliminates the need for dedicated reset logic at each sequential element, thereby reducing area and power consumption.
2Adaptability or versatility
If separate synchronous and asynchronous reset logic is implemented for each sequential logic element, then both synchronous and asynchronous reset functions are achieved, but the circuit complexity increases
Solution Approach 1:
The patent merges the control logic for synchronous and asynchronous resets into a single integrated unit. This unified approach reduces the total number of logic gates, multiplexers, and control signals required, thereby simplifying the overall circuit architecture while preserving the ability to perform both types of reset operations.
Solution Approach 2:
The reset unit is designed as a universal module that can generate both synchronous and asynchronous reset signals through a single control mechanism. This multi-functional design reduces the complexity associated with having separate dedicated circuits for each reset type, making the overall system easier to design, analyze, and implement.
3Adaptability or versatility
If additional gates are added to enable both synchronous and asynchronous reset, then reset versatility is improved, but power consumption increases
Solution Approach 1:
The patent combines synchronous and asynchronous reset generation into a single power-efficient unit. By sharing common logic resources and control mechanisms, the total number of active gates is reduced compared to having separate reset circuits, thereby lowering dynamic power consumption while maintaining the ability to perform both reset operations.
Solution Approach 2:
The unified reset unit uses a single set of control logic to generate both synchronous and asynchronous reset signals, eliminating the need for duplicate gate structures. This reduces the total switching activity and associated power consumption across the circuit while preserving full reset versatility.
Data Source
AI summary
An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting sequential logic. In one embodiment, reset logic generates a signal coupled to the at least one asynchronous reset input of the sequential logic to synchronously reset the sequential logic.