Sequential Mapping Table for Flash Memory Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices increase in size and complexity, existing memory mapping tables become inefficient due to large sizes exceeding available RAM, leading to increased latencies during operations like reading or writing, especially in devices with limited RAM for storing L2P tables.
Innovation Solution
The implementation of a reduced size representation of the L2P table, known as a sequential mapping table, which uses initial logical and physical addresses and the number of sequential corresponding addresses, significantly reducing the table size and eliminating the need for DRAM, thereby improving efficiency and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional L2P mapping tables are used to track virtual block to physical block associations, then complete mapping information is maintained, but the table size becomes excessively large exceeding available RAM capacity
Solution Approach 1:
The patent extracts only the essential mapping information needed for sequential operations. Instead of storing complete L2P mappings for all blocks, it extracts and stores only the initial logical block address and initial physical block address that define the mapping relationship, eliminating redundant mapping data while maintaining operational reliability.
Solution Approach 2:
The patent segments the mapping table into two parts: a compact sequential mapping table stored in RAM containing only initial address pairs, and the full L2P mapping information implicitly defined by the sequential relationship. This segmentation allows the critical mapping data to fit in limited RAM while maintaining complete mapping capability.
2Speed
If large L2P mapping tables are stored in RAM to ensure fast access, then data retrieval speed is improved, but the cost and complexity increase due to requiring larger DRAM capacity
Solution Approach 1:
The patent extracts only the minimal necessary data (initial logical block address and initial physical block address) needed to perform sequential mapping operations. This extracted information fits within limited DRAM capacity while maintaining fast access speeds for sequential operations, eliminating the need for large DRAM allocations.
Solution Approach 2:
The patent changes the data structure parameters from storing complete mapping pairs to storing only initial address pairs with implicit sequential relationships. This parameter change reduces the data volume by a factor equal to the sequential run length, allowing fast DRAM access with minimal memory capacity.
3Quantity of substance
If sequential mapping tables are implemented to reduce size, then DRAM requirements are eliminated, but the complexity of managing sequential address mappings increases
Solution Approach 1:
The sequential mapping table structure is self-describing and self-maintaining. Each entry contains the initial logical block address and initial physical block address, and the sequential relationship is inherently defined by the structure itself. The system automatically maintains consistency through the sequential mapping logic without requiring complex external management mechanisms.
Data Source
AI summary
Apparatus and methods are disclosed, including a sequential mapping table located within a flash memory array of a flash memory device. Selected examples include firmware in the flash memory device to load the sequential mapping table into a cache upon power and perform read and write operations using the sequential mapping table. Selected examples include firmware in the flash memory device to store an updated sequential mapping table into the flash memory array upon power down of the flash memory device.