Sequential Memory Write Restriction for Value-Checked Overwriting
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Solution Overview
Problem
Conventional semiconductor memory devices lack a system to restrict overwriting data based on specific conditions, such as writing only if the new data is larger or smaller than the existing data, leading to potential errors and damage in applications like consumer goods tracking.
Innovation Solution
A semiconductor memory device with a sequentially accessed non-volatile memory array that includes a write restricted storage address, a write data holding module, a data writing module, a reading module, and a control unit that determines whether the write data meets the value criteria before executing the write operation, ensuring that only data that meets the specified increase or decrease characteristics is written.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written to the memory array without value comparison, then writing speed is improved, but data integrity deteriorates
Solution Approach 1:
The patent applies preliminary action by comparing the value of write data with existing data before executing the write operation. The control unit reads existing data from the memory array, compares it with the write data, and determines whether to permit writing based on the comparison result. This pre-comparison mechanism ensures data integrity is maintained while allowing efficient writing when conditions are met.
2Reliability
If a write restriction system is implemented, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory device to autonomously perform value comparison and write restriction without requiring external control circuits or additional complexity. The control unit within the memory device itself reads existing data, compares it with write data, and automatically determines whether to permit writing. This self-contained approach maintains data integrity while avoiding increased device complexity.
3Ease of manufacture
If sequential access is used, then manufacturing cost is reduced, but access flexibility deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple storage areas, each with its own write restriction conditions. The control unit can selectively apply different value comparison rules to different segments, allowing sequential access efficiency to be maintained while providing flexible access control for specific data regions that require integrity protection.
Data Source
AI summary
When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.