Sequential Multitap Correlator for Fast GPS Acquisition

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Solution Overview

Problem

Conventional GPS receivers face challenges in achieving reduced time to first fix (TTFF) while maintaining a low gate count, especially in weak signal conditions, which is essential for E911 compliance and small form factor designs, as they require increased hardware complexity and longer acquisition times.

Innovation Solution

A low gate count sequential multitap correlator with a five-stage pipelined architecture is used, where the digital signal processor performs frequency estimation and the correlator conducts partial time delay correlation, reducing the number of accumulators and enabling faster signal detection across a wider frequency range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If multiple hardware blocks are used to perform correlation in parallel, then acquisition time is reduced, but gate count and device size increase

Engineering Contradiction:
Improveacquisition timeVSAvoidgate count
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the correlation process into multiple stages (first correlation stage, second correlation stage) with different tap configurations. The first stage uses fewer taps for initial correlation while the second stage uses more taps for refined correlation, allowing sequential processing that reduces overall gate count while maintaining acquisition performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically switches between different correlation configurations based on signal conditions. The system can transition between first and second correlation stages, adjusting the number of active taps and processing depth adaptively, which optimizes the balance between acquisition speed and hardware resource usage

Inventive Principle:
Principle #15Dynamics

2Reliability

If data length for weak signal analysis is increased, then signal detection capability is improved, but acquisition time increases

Engineering Contradiction:
Improveweak signal detection capabilityVSAvoidacquisition time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the correlation process into two stages: a first correlation stage that processes initial data segments to quickly identify potential signals, and a second correlation stage that processes additional data segments with higher tap counts for refined analysis of weak signals. This segmentation allows the system to achieve both fast acquisition and reliable weak signal detection without requiring all data to be processed simultaneously

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first correlation stage performs preliminary correlation processing with fewer taps to quickly establish initial signal detection and identify promising signal candidates. This preliminary action filters out obviously weak or incorrect signals before they undergo the more computationally intensive second correlation stage, thereby reducing overall acquisition time while maintaining detection capability for genuine weak signals

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7936846B2Low gate count sequential multitap correlator
Publication Date: 2011.05.03 ACCORD IDEATION PRIVATE LIMITED
  • US7936846B2 patent drawing
  • US7936846B2 patent drawing
  • US7936846B2 patent drawing

AI summary

A system and method of achieving a reduced time for first fix in a global positioning system receiver (GPS). The GPS receiver includes a low gate count sequential multitap correlator (102) in combination with a digital signal processor (106) and a down converter (101). The low gate count sequential multitap correlator (102) conducts sequential correlation on the incoming GPS signals using a multitapping and pipelining scheme. The multitapping process involves tapping the shift register and simultaneously correlating the signal samples and tapped chips. The pipelining process includes sampling data, mapping incoming samples, shifting carrier acquisition code, multiplying and accumulating the code and signal products. The digital signal processor conducts the frequency search.