Sequential Pipeline Stage Activation to Reduce Current Spikes
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Solution Overview
Problem
Integrated circuits with pipelining experience large current spikes due to simultaneous activation and deactivation of pipeline stages, leading to power supply noise and performance issues.
Innovation Solution
The integrated circuit includes a controller circuitry that loads static values into pipeline stages based on a clock enable signal and sequentially deactivates stages after a specified number of clock cycles, reducing current spikes by ensuring only the first stage draws significant current during activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipeline stages are activated simultaneously using a global clock enable signal, then the pipeline can quickly transition to active state, but large current spikes occur causing power supply noise and performance issues
Solution Approach 1:
The patent divides the simultaneous activation of all pipeline stages into sequential activation. Each pipeline stage is activated individually in sequence rather than all at once, which segments the current draw over multiple clock cycles. This is achieved by using individual enable signals for each stage that are activated sequentially, preventing the large simultaneous current spike that would occur with global enable activation.
Solution Approach 2:
The patent prepares pipeline stages for activation by setting their initial states beforehand. Before activation, each stage is pre-configured with appropriate initial values and states through reset and precharge operations. This preliminary preparation ensures that when stages are activated sequentially, they transition smoothly without causing large current spikes, while still achieving quick overall activation.
2Speed
If pipeline stages are deactivated simultaneously using a global clock enable signal, then the pipeline can quickly transition to inactive state, but large current spikes occur causing power supply noise
Solution Approach 1:
The patent segments the simultaneous deactivation of all pipeline stages into sequential deactivation. Each pipeline stage is deactivated individually in reverse sequence, which distributes the current reduction over multiple clock cycles rather than occurring all at once. This sequential approach eliminates the large simultaneous current drop that would cause power supply noise and voltage droops.
Solution Approach 2:
The patent prepares for deactivation by initiating a flush sequence that gradually clears data from pipeline stages before full deactivation. This preliminary flushing action ensures that stages are properly prepared for shutdown, maintaining data integrity while enabling smooth sequential deactivation without harmful current spikes.
3Object-generated harmful factors
If pipeline stages are flushed with static logic values, then current spikes are reduced during activation, but additional control circuitry and cycles are required
Solution Approach 1:
The patent implements a universal flush mechanism that serves multiple functions: it flushes pipeline stages during activation, maintains initial states, and supports sequential enablement. The same control circuitry that generates sequential enable signals also performs the flushing function by loading static logic values into stages. This multi-functionality reduces the need for separate dedicated flush circuitry, thereby limiting the increase in device complexity.
Solution Approach 2:
The pipeline stages perform their own flushing operation by loading static logic values into their internal registers and latches. Each stage is self-contained and can be independently initialized without requiring complex external control for each individual stage. This self-service approach simplifies the overall control architecture while achieving the current spike reduction benefit.
Data Source
AI summary
An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.