Sequential Power Gating Circuit for SoC Peak Current Control
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Solution Overview
Problem
Conventional system-on-a-chip (SoC) circuits experience increased peak current when power gating transistors are simultaneously turned ON, which can limit current for adjacent logic circuits and generate heat, degrading performance.
Innovation Solution
A power gating circuit with three sequentially turned ON PMOS transistors, controlled by NAND-gates, gradually increasing the internal power supply voltage to reduce peak current, with the first transistor being smaller than the second and third, and the second smaller than the third, to manage the timing of transistor activation based on voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If power gating transistors are simultaneously turned ON to provide power supply voltage, then power supply is established quickly, but peak current increases abruptly affecting adjacent logic circuits
Solution Approach 1:
The power gating transistors are divided into three separate groups (first, second, and third power gating transistors) that are turned ON sequentially rather than simultaneously. This segmentation of the power gating function across multiple transistor groups allows the power supply voltage to be established in stages, reducing the abrupt peak current that would occur if all transistors were turned ON at once.
Solution Approach 2:
The first power gating transistor is turned ON in advance before the second and third transistors. This preliminary action establishes an initial power supply voltage level that prepares the circuit for subsequent transistor activation, allowing adjacent logic circuits to gradually receive power and reducing the shock of simultaneous full-power activation.
2Object-generated harmful factors
If multiple power gating transistors are used to reduce peak current, then peak current is reduced, but device complexity increases
Solution Approach 1:
The control signals for the three power gating transistors are merged into a unified sequential control mechanism. The control unit generates coordinated control signals that turn ON the transistors in a predetermined sequence, combining multiple control functions into a single integrated control logic that manages all power gating transistors systematically.
Solution Approach 2:
The invention changes the operational parameters of the power gating transistors by assigning different turn-ON timing sequences to each transistor group. The first transistor group activates at an earlier time with different voltage characteristics compared to the second and third groups, which activate later. This parameter change in activation timing and voltage levels reduces peak current while maintaining manageable circuit complexity.
Data Source
AI summary
A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.