Sequential Read Optimization in Memory Sub-Systems
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Solution Overview
Problem
Existing memory sub-systems face inefficiencies in data transfer due to the inability to support sequential reads effectively, as they rely on slow non-volatile memory for logical-to-physical address translations, which increases read latency and does not optimize multi-LBA read commands.
Innovation Solution
Implementing a memory sub-system that caches a logical-to-physical (L2P) map with sequential assist values, allowing the host system to omit unnecessary translations and optimize read commands by splitting them into aligned sequences based on consecutive physical addresses, thereby reducing the burden on the memory system controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory sub-system uses non-volatile memory for logical-to-physical address translations, then data storage reliability is improved, but read latency increases and data transfer efficiency deteriorates
Solution Approach 1:
The patent segments the address translation process by maintaining separate L2P maps in different volatility domains. A first L2P map is stored in non-volatile memory for reliability, while a second L2P map is cached in volatile memory for fast access during read operations. This segmentation allows the system to leverage both non-volatile storage reliability and volatile memory speed, resolving the contradiction between data storage reliability and read latency.
2Measurement precision
If the memory sub-system performs full logical-to-physical address translations for each read command, then address mapping accuracy is improved, but processing overhead increases and productivity deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-translating logical block addresses to physical addresses and storing these mappings in both non-volatile and volatile L2P maps before read commands are issued. The volatile L2P map is populated in advance with address translations, so when read commands arrive, the system can perform quick lookups without performing full translations at the moment of reading. This preliminary preparation maintains address mapping accuracy while dramatically improving data transfer efficiency by eliminating on-the-fly translation overhead.
3Speed
If the memory sub-system caches the L2P map in volatile memory, then read speed is improved, but the system cannot maintain the cache across power cycles and loses translation information
Solution Approach 1:
The patent merges two L2P map storage mechanisms into a unified system: a first L2P map stored in non-volatile memory and a second L2P map stored in volatile memory. These two maps work together as a combined caching strategy where the non-volatile map provides persistent storage that survives power cycles, while the volatile map provides fast access during operation. The controller coordinates between these merged storage layers, copying relevant entries from the non-volatile map to the volatile map as needed, thus achieving both fast read speeds and cache persistence across power cycles.
Data Source
AI summary
An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.