Sequential Scan Interface Testing for Multi-Frequency Modules
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Solution Overview
Problem
Testing the interface between modules operating at different clock frequencies is challenging, as existing methods either test each module separately or together at a common frequency, failing to adequately assess timing-related faults such as transition faults.
Innovation Solution
Simultaneously testing two modules at their respective operating clock frequencies using a clock generation circuit that generates synchronized clock signals with specific latch edges, allowing for inter-module testing at the same speed as functional mode data transfer, thereby evaluating the interface logic at-speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If modules are tested separately at their respective clock frequencies, then timing-related faults can be detected, but inter-module operation cannot be adequately tested
Solution Approach 1:
The testing process is segmented into distinct phases: scan-in phase where test patterns are loaded at a first clock frequency, evaluation phase where modules operate at their respective functional clock frequencies, and scan-out phase where results are extracted. This segmentation allows each module to be tested at its native frequency while still enabling inter-module interface testing during the evaluation phase.
Solution Approach 2:
The system dynamically switches between different operational modes by controlling clock signals. The clock generation circuit dynamically adjusts clock frequencies based on the testing phase, enabling modules to operate at different frequencies during evaluation while maintaining synchronized scan operations during pattern loading and result extraction.
2Adaptability or versatility
If modules are tested together at a common clock frequency, then inter-module operation can be tested, but timing-related faults cannot be detected
Solution Approach 1:
The clock generation circuit dynamically adjusts clock frequencies based on the testing phase. During scan-in and scan-out phases, a common clock frequency is used for synchronized operations. During the evaluation phase, the system dynamically switches to allow modules to operate at their respective functional clock frequencies, enabling both inter-module testing and timing fault detection.
Solution Approach 2:
The system changes the clock frequency parameter based on the operational phase. Test patterns are scanned in at a first clock frequency, modules are evaluated at their respective functional frequencies, and results are scanned out at the first clock frequency. This parameter change allows the system to optimize for different testing objectives at different phases.
3Measurement precision
If sequential scan techniques are used to test inter-module operation, then comprehensive fault detection is possible, but the testing process becomes complex when modules operate at different frequencies
Solution Approach 1:
A clock generation circuit acts as an intermediary between the test pattern generator and the modules under test. This intermediary component manages the complexity of coordinating multiple clock frequencies by automatically generating appropriate clock signals for each phase of the testing process, simplifying the overall testing system architecture.
Solution Approach 2:
The clock generation circuit performs multiple functions: it generates the common clock frequency for scan-in operations, generates individual clock frequencies for each module during evaluation, and coordinates the transition between scan and evaluate modes. This multi-functionality reduces the need for separate dedicated circuits for each function.
Data Source
AI summary
According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).