Sequential Semiconductor Tester Module Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device testers, particularly Automatic Test Equipment (ATE), are expensive and inefficient, requiring long test times and limited to testing a single device at a time, while application environment testers lack the ability to test multiple devices simultaneously and maintain signal integrity.
Innovation Solution
A sequential semiconductor device tester is designed with a test pattern generating module that separates the function of generating test pattern data from executing the test, allowing for sequential testing of multiple devices under either application environment or ATE conditions, using a series-connected test execution modules to maintain signal integrity and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional ATE is used to test semiconductor devices, then testing capability is provided, but manufacturing cost is high and device complexity is large
Solution Approach 1:
The tester is divided into separate functional modules: a pattern generator module that creates test patterns and multiple test execution modules that perform actual testing. This segmentation allows each module to be independently designed, manufactured, and replaced, reducing overall system complexity and manufacturing cost while maintaining full testing capability.
Solution Approach 2:
The pattern generator module is designed to be universal and can generate test patterns for multiple types of semiconductor devices. The test execution modules can be configured to test different device types through software programming, eliminating the need for dedicated hardware for each device type and reducing overall system complexity.
2Productivity
If conventional ATE tests single device at a time, then signal integrity is maintained, but productivity is low and test time is long
Solution Approach 1:
Multiple test execution modules are combined into a single parallel testing system that can simultaneously test multiple semiconductor devices. Each module operates independently with its own test execution unit, allowing concurrent testing of multiple devices and significantly improving productivity while reducing total test time.
Solution Approach 2:
The system transitions from sequential testing (one device at a time) to parallel testing (multiple devices simultaneously) by adding a spatial dimension to the testing architecture. This dimensional change from time-sequential to space-parallel processing dramatically increases productivity without compromising signal integrity through proper module isolation.
3Ease of manufacture
If application environment tester is used, then cost is reduced, but ability to test multiple devices simultaneously is limited and signal integrity cannot be maintained
Solution Approach 1:
The system uses separate test execution modules that can be independently configured and connected to test multiple devices simultaneously. Each module maintains its own signal paths and testing capabilities, allowing parallel testing while controlling signal integrity through modular isolation, thus achieving both cost reduction and high productivity.
Solution Approach 2:
The test execution modules are designed with dynamic configurability through software control, allowing the system to adaptively test different device types and configurations. This dynamic nature enables the system to maintain signal integrity by configuring appropriate test parameters for each device while simultaneously testing multiple devices, achieving both low cost and high productivity.
Data Source
AI summary
A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.