Sequential Spacer Scheme for Semiconductor Pattern Fidelity
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in reliably creating small feature sizes due to the limitations of multiple lithography processes, which struggle to maintain precise spacing and pattern fidelity in transferring desired layouts to target layers.
Innovation Solution
A method involving the formation of spacers and sub-layouts to decompose a desired layout into multiple sub-layouts, allowing for precise separation and patterning of features, where spacers are used to maintain minimum spacing and facilitate etching of the target layer using multiple sub-layouts as masking features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple lithography processes are used to create smaller features, then the number of interconnected devices per unit area increases, but the precision of spacing and pattern fidelity deteriorates
Solution Approach 1:
The patent divides the desired layout into multiple sub-layouts, each corresponding to a specific lithography step. This segmentation allows complex patterns to be broken down into manageable components that can be fabricated with higher precision in separate steps, then combined through spacer formation and etching processes.
Solution Approach 2:
The patent employs preliminary actions by forming spacers around mandrels before the final pattern transfer. These spacers pre-establish the minimum spacing requirements between features, ensuring that when the target layer is etched, the desired pattern fidelity and spacing are maintained even as device density increases.
2Length of moving object
If multiple lithography processes are used to transfer desired layout, then feature size decreases, but the reliability of spacing maintenance deteriorates
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate between the lithographically defined mandrels and the final target layer pattern. These spacers act as self-aligned masks during etching, ensuring reliable spacing maintenance without requiring precise alignment between multiple lithography steps, thereby improving spacing reliability while enabling smaller feature sizes.
3Manufacturing precision
If spacers are formed around feature patterns, then minimum spacing between features is maintained, but the complexity of the fabrication process increases
Solution Approach 1:
The spacer formation process is self-aligning by default, as spacers are deposited conformally around mandrels and then etched back. This self-service mechanism automatically ensures minimum spacing without requiring additional alignment steps or complex process control, thereby achieving high spacing precision while limiting the increase in fabrication complexity.
Data Source
AI summary
Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.