Sequential Storage Circuitry NBTI Stress Reduction
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Solution Overview
Problem
Existing sequential storage circuitry in integrated circuits faces reliability issues due to stress buildup from Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI), which leads to device degradation and operational slowdown, particularly in low activity domains, and current techniques to mitigate this are costly and complex.
Innovation Solution
The design incorporates input and output circuitry that selectively flips the data value stored in a storage structure within the sequential storage circuitry, using control signals to generate an inverted version of the input data value, allowing periodic flipping of data even when static, thereby reducing stress buildup without requiring additional power, area, or architectural modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential storage circuitry operates in low activity domains with static bias, then device simplicity and low power consumption are maintained, but stress buildup from NBTI and PBTI causes threshold voltage degradation and device aging
Solution Approach 1:
The patent applies periodic action by introducing a control signal that periodically toggles the storage structure between storing the input data value and its inverted version. This periodic toggling prevents static bias conditions, anneals stress in the transistors, and reduces threshold voltage degradation without requiring continuous complex operations. The control signal activates at specific intervals to flip the stored value, maintaining device reliability while keeping the circuit simple during normal operation.
2Productivity
If device geometry is reduced to sub-45 nm, then integration density and productivity are improved, but intrinsic reliability limits are approached and device aging accelerates
Solution Approach 1:
The patent applies parameter changes by dynamically altering the stored data value parameter between its original and inverted states. This parameter toggling changes the bias conditions experienced by the transistors over time, preventing sustained stress accumulation. By periodically changing the stored value parameter, the circuit maintains higher reliability in scaled geometries where device aging is more severe, without sacrificing the high integration density achieved through sub-45 nm fabrication.
3Reliability
If over-design with increased margins is implemented, then resistance to Vt degradation is improved, but area and power consumption increase significantly
Solution Approach 1:
The patent applies self-service by enabling the storage circuitry to automatically mitigate its own threshold voltage degradation through periodic self-toggling. The control signal mechanism allows the circuit to periodically flip its stored value, which anneals internal stress and reduces Vt degradation without requiring external intervention or oversized device dimensions. This self-service approach maintains reliability without the area overhead of over-design.
4Reliability
If gate sizing is increased to reduce Vt degradation, then device threshold stability is improved, but power consumption and area increase
Solution Approach 1:
The patent applies periodic action to maintain threshold stability by periodically toggling the stored value in response to a control signal. This periodic operation prevents sustained negative or positive bias conditions that cause NBTI and PBTI effects, respectively. The approach maintains device threshold stability over time without requiring increased gate sizing, thereby avoiding the associated power consumption and area penalties.
Data Source
AI summary
Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry. More particularly, the output circuitry receives a second control signal derived from the first control signal, which causes the output circuitry to generate as said output data value an inverted version of the internal data value in the event that the input circuitry generated as the internal data value an inverted version of the input data value, and otherwise generates as the output data value the internal data value.