Sequential Storage Circuitry for On-the-Fly SEU Correction
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Solution Overview
Problem
Existing techniques for correcting single event upset errors in integrated circuits, such as those caused by neutron or alpha particle strikes, often require significant overhead in terms of area, power, and performance, and can detect false positives, necessitating system-level resets and power consumption.
Innovation Solution
A sequential storage circuit design that uses two additional storage elements and comparison circuitry to detect and correct single event upset errors on the fly, without changing the values stored in latches, by outputting the inverse of the erroneous value, thus avoiding the need for error correction feedback and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes or ECC are used to protect sequential storage circuits, then single bit flip errors can be corrected, but distributed bit failures in multiple sequential storage circuits cannot be corrected
Solution Approach 1:
The invention divides the error protection mechanism into distributed error detection units, each monitoring specific sequential storage circuits independently. This segmentation allows the system to handle distributed bit failures across multiple storage elements rather than treating them as a single error block, enabling ECC to be applied effectively to distributed errors in flip-flops and latches throughout the integrated circuit
2Quantity of substance
If process technology is shrunk to increase integration density, then more circuits can be packed, but susceptibility to soft errors increases
Solution Approach 1:
The sequential storage circuit is designed with built-in self-diagnostic capability through distributed error detection units that continuously monitor the storage elements. When a soft error occurs due to particle strikes, the affected circuit automatically detects and signals the error to the error correction logic, enabling self-correction without external intervention. This self-service mechanism allows high-density integration while maintaining reliability against increased SEU susceptibility
3Reliability
If redundancy is added to detect and correct errors, then error correction capability improves, but area overhead increases
Solution Approach 1:
The invention merges the error detection and correction functions into the existing sequential storage circuit structure. Error detection units are integrated alongside storage elements, and correction logic is combined with the clocking and control mechanisms. This merging approach provides comprehensive error protection while minimizing area overhead by utilizing shared resources and avoiding separate dedicated correction circuits
4Reliability
If system-level reset is used to flush errors, then error state can be cleared, but performance and power consumption are adversely affected
Solution Approach 1:
The invention implements continuous feedback monitoring through distributed error detection units that constantly check the state of sequential storage circuits. When an error is detected, the feedback mechanism immediately signals the error correction logic to correct the specific affected bit or flip-flop locally. This targeted feedback approach clears errors instantly without requiring system-level resets, maintaining high performance and avoiding unnecessary power consumption associated with global reset operations
Data Source
AI summary
Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.