Sequential Switch Control Circuit for Rush Current Reduction
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Solution Overview
Problem
Prior art switch circuits experience rush current issues due to simultaneous turn-on of switch units, leading to large instantaneous currents and potential function errors in logic circuits.
Innovation Solution
A switch controlling circuit utilizing a frequency programmable clock signal generator and registers to control switch devices sequentially, generating a frequency controllable clock signal that allows switch devices to turn on in order and stop the clock signal generation when all devices are on, thereby reducing rush current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If switch units turn on simultaneously to provide current to logic circuit, then power supply efficiency is improved, but large instantaneous current (rush current) is generated causing IR drop and function errors
Solution Approach 1:
The patent divides the simultaneous switching action into multiple sequential stages using a multi-stage register structure. Each switch unit is controlled by a separate stage register that activates in sequence, breaking the single simultaneous switching event into multiple time-separated events. This segmentation eliminates rush current while maintaining the ability to power multiple switch units.
Solution Approach 2:
The patent uses a frequency programmable clock signal generator to generate clock signals at a predetermined frequency before the actual switching operation. The multi-stage register structure is pre-configured to receive and process these clock signals, ensuring that switch units are activated in a controlled sequence rather than simultaneously. This preliminary action prepares the system to avoid rush current while maintaining productivity.
2Object-affected harmful factors
If multiple switch units are controlled to turn on in sequence to avoid rush current, then rush current is reduced, but circuit complexity increases due to additional control stages
Solution Approach 1:
The patent employs a universal multi-stage register structure where each stage register serves multiple functions: it stores the control signal, generates the clock signal at the appropriate stage, and controls the corresponding switch unit. This multi-functional design reduces the need for separate control circuits for each switch unit, thereby limiting the increase in overall circuit complexity while achieving sequential switching to eliminate rush current.
3Loss of energy
If clock signal generation stops when all switch devices are on, then energy consumption is reduced, but control precision must be maintained to ensure proper timing
Solution Approach 1:
The patent incorporates a feedback mechanism where the state of each switch unit is monitored and fed back to the clock signal generator. When all switch units are confirmed to be in the on state, the feedback signal triggers the clock signal generator to stop generating clock signals, reducing energy consumption. The feedback ensures that the stopping decision is based on precise detection of the actual switching state, maintaining timing precision while enabling energy savings.
Data Source
AI summary
A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first stage register, for receiving an input signal and the frequency controllable clock signal, and for outputting a first output signal, which is utilized to control a first switch device, according to the input signal and the frequency controllable clock signal; and a second stage register, for receiving the first output signal and the frequency controllable clock signal, and for outputting a second output signal, which is utilized to control a second switch device, according to the first output signal and the frequency controllable clock signal.