Sequential Memory Waveform Generator for Multi-Channel Signal Routing
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Solution Overview
Problem
Existing waveform generators face limitations in flexibility and efficiency, particularly in applications requiring a large number of channels, due to memory array size and signal routing issues, which hinder precise control and high resolution in ultrasound imaging and other transducer-driven systems.
Innovation Solution
A waveform generator system utilizing a system control unit and channels with sequential access memory, where each channel stores instruction words to generate waveforms, allowing for efficient sequential loading and generation of waveforms, and employing a two-dimensional shift register to manage waveform sequences, reducing memory requirements and improving signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory arrays are used to store waveform parameters, then waveform flexibility and resolution are improved, but device complexity and signal routing difficulty increase due to arrangement of contact pins and connection lines
Solution Approach 1:
The patent divides the waveform generation system into multiple independent channels, each with its own sequential access memory and control unit. This segmentation allows each channel to operate independently, reducing the complexity of signal routing while maintaining waveform flexibility. The memory arrays are organized into separate blocks for different channels, eliminating the need for complex cross-channel routing.
Solution Approach 2:
The patent introduces a time dimension to waveform storage by using sequential access memory with shift registers. Instead of storing complete waveform sequences in static memory arrays, the system loads waveform parameters sequentially over time, transforming the spatial memory access problem into a temporal sequence problem. This reduces the complexity of contact pin arrangement and connection lines.
2Adaptability or versatility
If multiple small blocks of memory are used for each channel, then channel independence is improved, but area occupation increases due to dedicated circuitry for each block
Solution Approach 1:
The patent implements shared resources among channels, including a common system control unit that manages all channels, shared clock signals, and common output routing. Each channel uses identical sequential access memory structures with the same control logic, allowing the system to serve multiple channels with a unified architecture rather than duplicating complete memory blocks for each channel.
Solution Approach 2:
The patent merges the control functions for multiple channels into a single system control unit that can sequentially or simultaneously manage all channels. The clock signals and control logic are combined and distributed to all channels, reducing the total area occupied by dedicated circuitry while maintaining channel independence through logical separation rather than physical isolation.
3Measurement precision
If high frequency system clock is used, then time resolution is improved, but waveform generation complexity increases
Solution Approach 1:
The patent replaces complex analog waveform generation circuits with digital sequential access memory and shift register systems. The high frequency clock drives the sequential loading of waveform parameters from memory through shift registers, generating precise waveforms through digital logic rather than analog circuitry. This substitution maintains high time resolution while reducing overall system complexity through standardized digital components.
Data Source
AI summary
A waveform generator includes a system control unit and signal channels controlled by the system control unit and configured to supply driving signals for driving a respective transducer of an array of transducers. Each signal channel includes a sequential access memory having rows, where each row contains an instruction word configured to generate a respective step of a waveform to be generated. A memory output of the sequential access memory is defined by an output row at a fixed location. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit that is configured to sequentially move the content of the sequential access memory, based on the instruction word currently at the memory output, so that sequences of instruction words are provided at the output row.