Sequential Word Line Erase for 3D NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing erase techniques for 3D non-volatile memory devices, such as selective word line erase and all word line erase, face challenges in achieving uniform erase distribution and efficient erase speed due to complex interactions between channel potential, tunneling speed, and gate-induced drain leakage (GIDL) current, particularly in 3D stacked NAND structures with cylindrical memory holes.
Innovation Solution
The proposed sequential word line erase technique initiates erasing of storage elements in a sequence, with shifted start times and varying erase periods based on their position within the NAND string, ensuring all elements reach a common pre-charge level, thereby optimizing charging and erasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective word line erase is used, then erase uniformity is improved, but erase speed deteriorates
Solution Approach 1:
The patent segments the erase operation into multiple phases with different word line selection patterns. First, odd word lines are erased, then even word lines are erased. This segmentation allows parallel processing of multiple word lines while maintaining uniformity within each group, resolving the contradiction between erase uniformity and speed.
Solution Approach 2:
The patent applies preliminary actions by performing specific voltage configurations and pre-charge operations before the actual erase. The channel is pre-charged to a first voltage level, and control gates are configured to specific voltages before erasing each group of word lines. This preliminary preparation ensures uniform erase characteristics across all word lines while enabling faster parallel processing.
2Productivity
If all word line erase is used, then erase speed is improved, but erase uniformity deteriorates
Solution Approach 1:
The patent applies local quality by using different erase configurations for different groups of word lines. Odd word lines and even word lines are erased in separate phases with tailored voltage configurations. This allows optimization of erase uniformity for each group while maintaining high overall erase speed through parallel processing capability.
Solution Approach 2:
The patent uses periodic action by alternating between erasing odd word lines and even word lines in separate phases. This periodic approach ensures that each group receives dedicated erase attention with optimized voltage configurations, maintaining uniformity while achieving fast overall erase through the periodic alternation between groups.
3Productivity
If sequential word line erase is used, then erase speed is improved, but device complexity increases
Solution Approach 1:
The patent segments word lines into odd and even groups that can be controlled independently. This segmentation simplifies the control logic by creating two distinct control paths rather than managing each word line individually, reducing the apparent complexity while enabling parallel processing for faster erase.
Solution Approach 2:
The patent merges the control of multiple word lines within each group (odd lines together, even lines together) under unified voltage configurations. This merging reduces control complexity by treating groups as single units while still achieving parallel erase of multiple individual word lines within each group.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a tightened erase distribution, enhanced erase speed, improved channel potential boosting, and increased reliability of select gate transistors, leading to faster and more uniform erasure of storage elements across the memory device.
Implementation Method 1
complex interactions between channel potential, tunneling speed, and gate-induced drain leakage (GIDL) current
Implementation Method 2
complex interactions between channel potential, tunneling speed, and gate-induced drain leakage (GIDL) current
Data Source
AI summary
An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.